Kiyoung Choi - RankMe

210 papers A* 17A 32B 4C 17Misc 5Journal 66Unranked 65

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Zero Wrench Control via Wrench Disturbance Observer for Learning-free Peg-in-hole Assembly. CoRR Kiyoung Choi, Juwon Jeong, Sehoon Oh
2025	A*	`conf`	Low Impedance Rendering Toward Safe Human-Robot Interaction. HRI Wonbum Yun, Kiyoung Choi, Junyoung Kim, Sehoon Oh, Hyun-Joon Chung
2025	A*	`conf`	Robust Orientation Control of Robot Manipulator Using Orientation Disturbance Observer. ICRA Kiyoung Choi, Junho Song, Wonbum Yun, Sehoon Oh
2024	A	`conf`	Identification of Flexible Joint Robot Inertia Matrix Using Frequency Response Analysis. IROS Kiyoung Choi, Junho Song, Wonbum Yun, Deokjin Lee, Sehoon Oh
2024	—	`conf`	Identification of Flexible Joint Robot Inertia Matrix Using Frequency Response Analysis. ISIE Kiyoung Choi, Junho Song, Wonbum Yun, Deokjin Lee, Sehoon Oh
2023	—	`conf`	ExSLeR: Development of a Robotic Arm for Human Skill Learning. AIM Deokjin Lee, Kiyoung Choi, Junyoung Kim, Wonbum Yun, Taehoon Kim, Kanghyun Nam, Sehoon Oh
2023	J	`jnl`	Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. CoRR Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi
2022	J	`jnl`	ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator. IEEE Trans. Computers Namhyung Kim, Hanmin Park, Dongwoo Lee, Sungbum Kang, Jinho Lee, Kiyoung Choi
2022	C	`conf`	Human-Robot Interaction Force based Power Assistive Algorithm of Upper Limb Exoskeleton Robots Driven by a Series Elastic Actuator. IECON Deokjin Lee, Kiyoung Choi, Wonbum Yun, Sehoon Oh
2021	A*	`conf`	GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. HPCA Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, Jinho Lee
2021	J	`jnl`	GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. CoRR Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, Jinho Lee
2020	J	`jnl`	Aging Compensation With Dynamic Computation Approximation. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Heesu Kim, Jongho Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, Kiyoung Choi, Hanmin Park
2019	A*	`conf`	Acceleration of DNN Backward Propagation by Selective Computation of Gradients. DAC Gunhee Lee, Hanmin Park, Namhyung Kim, Joonsang Yu, Sujeong Jo, Kiyoung Choi
2019	C	`conf`	Aging Gracefully with Approximation. ISCAS Jongho Kim, Heesu Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, Kiyoung Choi
2019	—	`conf`	An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network. ISOCC Chaeun Lee, Jaehyun Kim, Kiyoung Choi
2019	J	`jnl`	Autoencoder-Based Incremental Class Learning without Retraining on Old Data. CoRR Euntae Choi, Kyungmi Lee, Kiyoung Choi
2019	—	`conf`	Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators. ASP-DAC Hanmin Park, Kiyoung Choi
2019	A*	`conf`	Network Recasting: A Universal Method for Network Architecture Transformation. AAAI Joonsang Yu, Sungbum Kang, Kiyoung Choi
2019	A	`conf`	VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks. ISLPED Jaehyun Kim, Chaeun Lee, Jihun Kim, Yumin Kim, Cheol Seong Hwang, Kiyoung Choi
2018	J	`jnl`	An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aidyn Zhakatayev, Kyounghoon Kim, Kiyoung Choi, Jongeun Lee
2018	—	`conf`	Architectures and algorithms for user customization of CNNs. ASP-DAC Barend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi
2018	J	`jnl`	Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. ACM Trans. Archit. Code Optim. Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sánchez, Donghoon Yoo, Soojung Ryu
2018	A	`conf`	ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator. ICS Dongwoo Lee, Sungbum Kang, Kiyoung Choi
2018	J	`jnl`	Deep neural networks with weighted spikes. Neurocomputing Jaehyun Kim, Heesu Kim, Subin Huh, Jinho Lee, Kiyoung Choi
2018	J	`jnl`	Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation. IEEE Trans. Very Large Scale Integr. Syst. Jongho Kim, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung-Hwan Choi
2018	—	`conf`	Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks. ISOCC Jaehyun Kim, Chaeun Lee, Kiyoung Choi
2018	J	`jnl`	Network Recasting: A Universal Method for Network Architecture Transformation. CoRR Joonsang Yu, Sungbum Kang, Kiyoung Choi
2018	—	`conf`	Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators. ISOCC Hossein Moradian, Sujeong Jo, Kiyoung Choi
2018	—	`conf`	Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands. APSIPA Heesu Kim, Euntae Choi, Kiyoung Choi
2018	—	`conf`	Tapered-Ratio Compression for Residual Network. ISOCC Sungbum Kang, Joonsang Yu, Kiyoung Choi
2018	C	`conf`	Training Neural Networks with Low Precision Dynamic Fixed-Point. ICCD Sujeong Jo, Hanmin Park, Gunhee Lee, Kiyoung Choi
2017	—	`conf`	A new stochastic mutiplier for deep neural networks. ISOCC Subin Huh, Joonsang Yu, Kiyoung Choi
2017	A	`conf`	A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures. CGO Bernhard Egger, Hochan Lee, Duseok Kang, Mansureh S. Moghaddam, Youngchul Cho, Yeonbok Lee, Sukjin Kim, Soonhoi Ha, Kiyoung Choi
2017	C	`conf`	Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks. ICCD Joonsang Yu, Kyounghoon Kim, Jongeun Lee, Kiyoung Choi
2017	J	`jnl`	Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hyunjik Song, Kiyoung Choi
2017	A	`conf`	Design space exploration of FPGA accelerators for convolutional neural networks. DATE Atul Rahman, Sangyun Oh, Jongeun Lee, Kiyoung Choi
2017	J	`jnl`	Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch. ACM Trans. Archit. Code Optim. Dongwoo Lee, Sang-Heon Lee, Soojung Ryu, Kiyoung Choi
2017	J	`jnl`	Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares. IEEE Trans. Very Large Scale Integr. Syst. Jinho Lee, Jongwook Chung, Jung Ho Ahn, Kiyoung Choi
2017	J	`jnl`	ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator. Proc. VLDB Endow. Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark Nutter, Damir A. Jamsek
2017	—	`conf`	FPGA implementation of convolutional neural network based on stochastic computing. FPT Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeon Uk Sim, Jongeun Lee, Kiyoung Choi
2017	—	`conf`	Hybrid spiking-stochastic Deep Neural Network. VLSI-DAT Heesu Kim, Joonsang Yu, Kiyoung Choi
2017	Misc	`conf`	Incremental training of CNNs for user customization: work-in-progress. CASES Mansureh S. Moghaddam, Barend Harris, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi
2017	J	`jnl`	Optimal mapping of program overlays onto many-core platforms with limited memory capacity. Des. Autom. Embed. Syst. Mansureh Shahraki Moghaddam, M. Balakrishnan, Kiyoung Choi
2017	—	`ch.`	Reconfigurable Architectures. Handbook of Hardware/Software Codesign Mansureh Shahraki Moghaddam, Jae-Min Cho, Kiyoung Choi
2017	—	`conf`	Scalable stochastic-computing accelerator for convolutional neural networks. ASP-DAC Hyeon Uk Sim, Dong Nguyen, Jongeun Lee, Kiyoung Choi
2017	C	`conf`	Synthesis of multi-variate stochastic computing circuits. VLSI-SoC Kyounghoon Kim, Kiyoung Choi
2016	J	`jnl`	A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers. Pattern Recognit. Kyounghoon Kim, Helin Lin, Jin Young Choi, Kiyoung Choi
2016	—	`conf`	A new approach to binarizing neural networks. ISOCC Jungwoo Seo, Joonsang Yu, Jongeun Lee, Kiyoung Choi
2016	J	`jnl`	AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy. ACM Trans. Archit. Code Optim. Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
2016	A	`conf`	Adaptive delay monitoring for wide voltage-range operation. DATE Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung Yun Choi
2016	J	`jnl`	Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip. IET Comput. Digit. Tech. Hanmin Park, Kiyoung Choi
2016	—	`conf`	An energy-efficient random number generator for stochastic circuits. ASP-DAC Kyounghoon Kim, Jongeun Lee, Kiyoung Choi
2016	A	`conf`	Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic. DATE Jinho Lee, Jung Ho Ahn, Kiyoung Choi
2016	C	`conf`	Dynamic clock synchronization scheme between voltage domains in multi-core architecture. VLSI-SoC Jaehyun Kim, Kiyoung Choi, Sang-Heon Lee, Soojung Ryu
2016	A*	`conf`	Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks. DAC Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi
2016	A	`conf`	Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array. DATE Atul Rahman, Jongeun Lee, Kiyoung Choi
2016	J	`jnl`	Exploration of trade-offs in the design of volatile STT-RAM cache. J. Syst. Archit. Namhyung Kim, Kiyoung Choi
2016	J	`jnl`	Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. IEEE Trans. Very Large Scale Integr. Syst. Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
2016	J	`jnl`	Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture. IEEE Trans. Computers Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
2016	—	`ed.`	VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers VLSI-SoC (Selected Papers) Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis
2015	A*	`conf`	A scalable processing-in-memory accelerator for parallel graph processing. ISCA Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi
2015	C	`conf`	Dynamic error tracking and supply voltage adjustment for low power. VLSI-SoC Pierre Nicolas-Nicolaz, Kiyoung Choi
2015	C	`conf`	Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. VLSI-SoC Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi
2015	J	`jnl`	Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing. IEEE Trans. Multi Scale Comput. Syst. Yiran Chen, Kiyoung Choi, Weisheng Zhao
2015	C	`conf`	Message from the general chairs. VLSI-SoC Naehyuck Chang, Kiyoung Choi
2015	A*	`conf`	PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture. ISCA Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi
2015	J	`jnl`	REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections. ACM J. Emerg. Technol. Comput. Syst. Jinho Lee, Kyungsu Kang, Kiyoung Choi
2015	—	`conf`	THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures. ASP-DAC Jinho Lee, Junwhan Ahn, Kiyoung Choi, Kyungsu Kang
2014	—	`conf`	An FPGA implementation of high-throughput key-value store using Bloom filter. VLSI-DAT Jae Min Cho, Kiyoung Choi
2014	B	`conf`	Concept-aware ensemble system for pedestrian detection. Intelligent Vehicles Symposium Helin Lin, Kyounghoon Kim, Kiyoung Choi
2014	J	`jnl`	Configurable range memory for effective data reuse on programmable accelerators. ACM Trans. Design Autom. Electr. Syst. Jongeun Lee, Seongseok Seo, Jong Kyung Paek, Kiyoung Choi
2014	J	`jnl`	Critical-path-aware high-level synthesis with distributed controller for fast timing closure. ACM Trans. Design Autom. Electr. Syst. Seokhyun Lee, Kiyoung Choi
2014	A*	`conf`	DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture. HPCA Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
2014	J	`jnl`	Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. Integr. Manhwee Jo, Dongwook Lee, Kyuseung Han, Kiyoung Choi
2014	A*	`conf`	Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes. DAC Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
2014	—	`conf`	Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture. VLSI-SoC (Selected Papers) Dongwoo Lee, Kiyoung Choi
2014	C	`conf`	Energy-efficient partitioning of hybrid caches in multi-core architecture. VLSI-SoC Dongwoo Lee, Kiyoung Choi
2014	J	`jnl`	Introduction to the Special Issue on the 11 ACM Trans. Reconfigurable Technol. Syst. Jason Helge Anderson, Kiyoung Choi
2014	J	`jnl`	LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology. IEEE Trans. Very Large Scale Integr. Syst. Junwhan Ahn, Kiyoung Choi
2014	—	`conf`	Leveraging parallelism in the presence of control flow on CGRAs. ASP-DAC Jihyun Ryoo, Kyuseung Han, Kiyoung Choi
2014	J	`jnl`	Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture. IEEE Trans. Dependable Secur. Comput. Kyuseung Han, Ganghee Lee, Kiyoung Choi
2014	—	`conf`	Tree-Mesh Heterogeneous Topology for Low-Latency NoC. NoCArc@MICRO Sungju Han, Jinho Lee, Kiyoung Choi
2013	—	`conf`	A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections. NOCS Jinho Lee, Kiyoung Choi
2013	J	`jnl`	CPU-based speed acceleration techniques for shear warp volume rendering. Multim. Tools Appl. Kiyoung Choi, Sung-Up Jo, HwaMin Lee, Changsung Jeong
2013	A	`conf`	Compiling control-intensive loops for CGRAs with state-based full predication. DATE Kyuseung Han, Kiyoung Choi, Jongeun Lee
2013	—	`conf`	Deflection routing in 3D Network-on-Chip with TSV serialization. ASP-DAC Jinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi
2013	J	`jnl`	Deflection routing in 3D network-on-chip with limited vertical bandwidth. ACM Trans. Design Autom. Electr. Syst. Jinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi
2013	—	`conf`	Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture. MUE Manhwee Jo, Kyuseung Han, Kiyoung Choi
2013	J	`jnl`	Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Junwhan Ahn, Kiyoung Choi
2013	J	`jnl`	Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinho Lee, Moo-Kyoung Chung, Yeon-Gon Cho, Soojung Ryu, Jung Ho Ahn, Kiyoung Choi
2013	J	`jnl`	Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. ACM Trans. Archit. Code Optim. Kyuseung Han, Junwhan Ahn, Kiyoung Choi
2013	—	`conf`	Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. ASP-DAC Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
2013	—	`conf`	Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth. NoCArc@MICRO Gunhee Lee, Jinho Lee, Kiyoung Choi
2013	A	`conf`	Write intensity prediction for energy-efficient non-volatile caches. ISLPED Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
2012	—	`conf`	A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem. ISOCC Dongwoo Lee, Junwhan Ahn, Kiyoung Choi
2012	J	`jnl`	Active Memory Processor for Network-on-Chip-Based Architecture. IEEE Trans. Computers Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi
2012	C	`conf`	An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth. VLSI-SoC Mingyang Zhu, Jinho Lee, Kiyoung Choi
2012	J	`jnl`	ESL Design Methodology. J. Electr. Comput. Eng. Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang
2012	J	`jnl`	Exploiting New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. John Kim, Kiyoung Choi, Gabriel H. Loh
2012	J	`jnl`	Guest Editorial New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. Kiyoung Choi, John Kim, Gabriel H. Loh
2012	C	`conf`	Lower-bits cache for low power STT-RAM caches. ISCAS Junwhan Ahn, Kiyoung Choi
2012	—	`conf`	Memory-aware mapping and scheduling of tasks and communications on many-core SoC. ASP-DAC Jinho Lee, Kiyoung Choi
2012	—	`conf`	Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips. NoCArc@MICRO Hanmin Park, Kiyoung Choi
2012	—	`conf`	Resource-shared custom instruction generation under performance/area constraints. ISSoC Di Wu, Junwhan Ahn, Imyong Lee, Kiyoung Choi
2012	A	`conf`	State-based full predication for low power coarse-grained reconfigurable architecture. DATE Kyuseung Han, Seongsik Park, Kiyoung Choi
2011	—	`conf`	3D network-on-chip with wireless links through inductive coupling. ISOCC Jinho Lee, Mingyang Zhu, Kiyoung Choi, Jung Ho Ahn, Rohit Sharma
2011	—	`conf`	A host-accelerator communication architecture design for efficient binary acceleration. ISOCC Yangsu Kim, Kyuseung Han, Kiyoung Choi
2011	—	`conf`	A polynomial-time custom instruction identification algorithm based on dynamic programming. ASP-DAC Junwhan Ahn, Imyong Lee, Kiyoung Choi
2011	Misc	`conf`	An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. CODES+ISSS Junwhan Ahn, Kiyoung Choi
2011	—	`conf`	CRM: Configurable Range Memory for Fast Reconfigurable Computing. IPDPS Workshops Jong Kyung Paek, Jong-eun Lee, Kiyoung Choi
2011	J	`jnl`	Coarse-Grained Reconfigurable Array: Architecture and Application Mapping. IPSJ Trans. Syst. LSI Des. Methodol. Kiyoung Choi
2011	A	`conf`	High-level synthesis with distributed controller for fast timing closure. ICCAD Seokhyun Lee, Kiyoung Choi
2011	J	`jnl`	Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ganghee Lee, Kiyoung Choi, Nikil D. Dutt
2011	—	`conf`	Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane. NEMS Jae Hong Park, Kiyoung Choi, Dong-Yeon Lee, Jaesool Shim, Tae Song Kim
2011	—	`conf`	Simulated annealing-based diffusive load balancing on many-core SoC. ICAC Hyunjik Song, Kiyoung Choi
2010	—	`conf`	Acceleration of control flow on CGRA using advanced predicated execution. FPT Kyuseung Han, Jong Kyung Paek, Kiyoung Choi
2010	—	`conf`	Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. IPDPS Workshops Ganghee Lee, Kyungwook Chang, Kiyoung Choi
2010	J	`jnl`	Binary acceleration using coarse-grained reconfigurable architecture. SIGARCH Comput. Archit. News Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee
2010	J	`jnl`	Communication architecture design for reconfigurable multimedia SoC platform. Des. Autom. Embed. Syst. Ganghee Lee, Yongjin Ahn, Seokhyun Lee, Jeongki Son, Kiwook Yoon, Kiyoung Choi
2010	J	`jnl`	Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. Yoonjin Kim, Rabi N. Mahapatra, Kiyoung Choi
2010	—	`conf`	Memory-Centric Communication Architecture for Reconfigurable Computing. ARC Kyungwook Chang, Kiyoung Choi
2010	—	`conf`	Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. ARC Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt
2010	—	`conf`	Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture. AHS Ganghee Lee, Kiyoung Choi
2009	—	`conf`	Coarse-grained reconfigurable architecture for multiple application domains: a case study. ICHIT Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, Kiwook Yoon
2009	—	`conf`	Code decomposition and recomposition for enhancing embedded software performance. ASP-DAC Youngchul Cho, Kiyoung Choi
2009	J	`jnl`	Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture. IEEE Trans. Very Large Scale Integr. Syst. Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, Kiyoung Choi
2009	A*	`conf`	Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. DAC Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi
2009	J	`jnl`	Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. IEEE Trans. Very Large Scale Integr. Syst. Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi
2008	—	`conf`	A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. ISVLSI V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi
2008	A	`conf`	Entry control in network-on-chip for memory power reduction. ISLPED Dongwook Lee, Sungjoo Yoo, Kiyoung Choi
2008	J	`jnl`	Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. Int. J. Embed. Syst. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2008	J	`jnl`	Introduction to embedded systems week 2006 special issue. ACM Trans. Embed. Comput. Syst. Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi
2008	—	`ed.`	Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008 ASP-DAC Chong-Min Kyung, Kiyoung Choi, Soonhoi Ha
2008	J	`jnl`	SoCDAL: System-on-chip design AcceLerator. ACM Trans. Design Autom. Electr. Syst. Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Jun-hee Yoo, Kiyoung Choi, Xingguang Feng
2007	—	`conf`	Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. ICSAMOS Ganghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi
2007	B	`conf`	Buffer Size Reduction through Control-Flow Decomposition. RTCSA Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi
2007	—	`conf`	Communication Architecture Synthesis of Cascaded Bus Matrix. ASP-DAC Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi
2007	J	`jnl`	Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction. Des. Autom. Embed. Syst. Jinyong Jung, Sungjoo Yoo, Kiyoung Choi
2007	—	`conf`	Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture. SoCC Manhwee Jo, V. K. Prasad Arava, Hoonmo Yang, Kiyoung Choi
2007	J	`jnl`	Instruction set synthesis with efficient instruction encoding for configurable processors. ACM Trans. Design Autom. Electr. Syst. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2007	C	`conf`	Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. IEEE International Workshop on Rapid System Prototyping Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya
2007	—	`conf`	Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation. ASAP Imyong Lee, Dongwook Lee, Kiyoung Choi
2007	Misc	`ed.`	Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 CODES+ISSS Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich
2007	J	`jnl`	Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization CoRR Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi
2007	J	`jnl`	Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Des. Autom. Embed. Syst. Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi
2006	A	`conf`	A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. DATE Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi
2006	A	`conf`	Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. ISLPED Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek
2006	Misc	`ed.`	Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006 CODES+ISSS Reinaldo A. Bergamaschi, Kiyoung Choi
2006	—	`conf`	Worst case execution time analysis for synthesized hardware. ASP-DAC Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi
2005	J	`jnl`	Pipelining with common operands for power-efficient linear systems. IEEE Trans. Very Large Scale Integr. Syst. Daehong Kim, Dongwan Shin, Kiyoung Choi
2005	A	`conf`	Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. DATE Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi
2005	—	`conf`	Scheduler implementation in MP SoC design. ASP-DAC Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2004	A*	`conf`	A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints. ICRA Whee Kuk Kim, Kiyoung Choi, Byung-Ju Yi
2004	—	`conf`	Application-specific configuration of multithreaded processor architecture for embedded applications. ISCAS (2) Mary Kiemb, Kiyoung Choi
2004	Misc	`conf`	Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. CASES Mary Kiemb, Kiyoung Choi
2004	A	`ed.`	Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 ISLPED Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy
2003	J	`jnl`	An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. Des. Autom. Embed. Syst. Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae
2003	B	`conf`	An algorithm for mapping loops onto coarse-grained reconfigurable architectures. LCTES Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2003	J	`jnl`	Compilation Approach for Coarse-Grained Reconfigurable Architectures. IEEE Des. Test Comput. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2003	J	`jnl`	Configurable Processors for Embedded Computing. Computer Nikil D. Dutt, Kiyoung Choi
2003	A	`conf`	Energy-efficient instruction set synthesis for application-specific processors. ISLPED Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2003	—	`conf`	Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. ASAP Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2003	—	`ch.`	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. Embedded Software for SoC Youngchul Cho, Ganghee Lee, Kiyoung Choi, Sungjoo Yoo, Nacer-Eddine Zergainoh
2003	A	`conf`	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. DATE Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh
2002	A	`conf`	An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. ISLPED Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo
2002	A	`conf`	Efficient instruction encoding for automatic instruction set design of configurable ASIPs. ICCAD Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2002	—	`conf`	Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. CODES Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi
2001	—	`conf`	Area-efficient buffer binding based on a novel two-port FIFO structure. CODES Kyoungseok Rha, Kiyoung Choi
2001	A	`conf`	Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. ICCAD Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi
2001	—	`conf`	High-level synthesis under multi-cycle interconnect delay. ASP-DAC Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi
2001	A	`conf`	Low power pipelining of linear systems: a common operand centric approach. ISLPED Daehong Kim, Dongwan Shin, Kiyoung Choi
2001	J	`jnl`	Narrow bus encoding for low-power DSP systems. IEEE Trans. Very Large Scale Integr. Syst. Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang
2001	J	`jnl`	Partial bus-invert coding for power optimization of application-specific systems. IEEE Trans. Very Large Scale Integr. Syst. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
2001	A	`conf`	Performance improvement of multi-processor systems cosimulation based on SW analysis. DATE Jinyong Jung, Sungjoo Yoo, Kiyoung Choi
2001	J	`jnl`	Performance-driven high-level synthesis with bit-level chaining andclock selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sanghun Park, Kiyoung Choi
2001	J	`jnl`	Power-conscious Scheduling for Real-time Embedded Systems Design. VLSI Design Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
2001	—	`conf`	Scheduling-based code size reduction in processors with indirect addressing mode. CODES Sungtaek Lim, Jihong Kim, Kiyoung Choi
2000	C	`conf`	A new cost model for high-level power optimization and its application. ISCAS Taekyoon Ahn, Kiyoung Choi, Ki-Hyun Kim, Seong-Kwan Hon
2000	A	`conf`	Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. DATE Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi
2000	—	`conf`	Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. ASP-DAC Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi
2000	A	`conf`	Low power self-timed Radix-2 division (poster session). ISLPED Jae-Hee Won, Kiyoung Choi
2000	—	`conf`	Narrow bus encoding for low power systems. ASP-DAC Youngsoo Shin, Kiyoung Choi
2000	J	`jnl`	Optimizing Timed Cosimulation by Hybrid Synchronization. Des. Autom. Embed. Syst. Sungjoo Yoo, Kiyoung Choi
2000	—	`conf`	Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. CODES Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi
2000	J	`jnl`	Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. IEEE Trans. Very Large Scale Integr. Syst. Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha
2000	A	`conf`	Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
2000	A	`conf`	Power minimization of functional units partially guarded computation. ISLPED Junghwan Choi, Jinhwan Jeon, Kiyoung Choi
2000	A*	`conf`	Schedulability-driven performance analysis of multiple mode embedded real-time systems. DAC Youngsoo Shin, Daehong Kim, Kiyoung Choi
1999	A	`conf`	Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. FPGA Byungil Jeong, Sungjoo Yoo, Kiyoung Choi
1999	—	`conf`	Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. CODES Sungjoo Yoo, Kiyoung Choi
1999	A*	`conf`	Performance-Driven Scheduling with Bit-Level Chaining. DAC Sanghun Park, Kiyoung Choi
1999	A*	`conf`	Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. DAC Youngsoo Shin, Kiyoung Choi
1998	J	`jnl`	An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping. Des. Autom. Embed. Syst. Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Kiyoung Choi
1998	—	`conf`	Loop Pipelining in Hardware-Software Partitioning. ASP-DAC Jinhwan Jeon, Kiyoung Choi
1998	—	`conf`	Optimistic distributed timed cosimulation based on thread simulation model. CODES Sungjoo Yoo, Kiyoung Choi
1998	A	`conf`	Partial bus-invert coding for power optimization of system level bus. ISLPED Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
1998	—	`conf`	Rate Assignment for Embedded Reactive Real-Time Systems. EUROMICRO Youngsoo Shin, Kiyoung Choi
1997	—	`conf`	Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. CODES Youngsoo Shin, Kiyoung Choi
1997	A	`conf`	Low power high level synthesis by increasing data correlation. ISLPED Dongwan Shin, Kiyoung Choi
1997	A*	`conf`	Power-conscious High Level Synthesis Using Loop Folding. DAC Daehong Kim, Kiyoung Choi
1996	C	`conf`	An integrated hardware-software cosimulation environment with automated interface generation. RSP Kyuseok Kim, Yongjoo Kim, Youngsoo Shin, Kiyoung Choi
1996	B	`conf`	Hardware-Software Codesign of Resource-Constrained Real-Time Systems. RTCSA Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, Kiyoung Choi
1996	J	`jnl`	Self-timed divider based on RSD number system. IEEE Trans. Very Large Scale Integr. Syst. KiJong Lee, Kiyoung Choi
1996	A	`conf`	Software synthesis through task decomposition by dependency analysis. ICCAD Youngsoo Shin, Kiyoung Choi
1996	—	`conf`	Thread-based software synthesis for embedded system design. ED&TC Youngsoo Shin, Kiyoung Choi
1995	—	`conf`	An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. ASP-DAC Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha
1995	C	`conf`	Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. ISCAS Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi
1994	C	`conf`	A Self-Timed Divider Using RSD Number System. ICCD Kiyoung Choi, KiJong Lee, Jun-Woo Kang
1988	J	`jnl`	Fast functional simulation: an incremental approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sun Young Hwang, Tom Blank, Kiyoung Choi
1988	A*	`conf`	Incremental-in-time Algorithm for Digital Simulation. DAC Kiyoung Choi, Sun Young Hwang, Tom Blank