Kiyoshi Oguri - RankMe

76 papers A 3B 12C 6Misc 5Journal 19Unranked 31

Year	Rank	Type	Title / Venue / Authors
2019	Misc	`conf`	Pipelined FPGA Implementation of a Wave-Front-Fetch Graph Cut System. CISIS Naofumi Yoshinaga, Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri
2018	J	`jnl`	A new stereo formulation not using pixel and disparity models. CoRR Kiyoshi Oguri, Yuichiro Shibata
2018	—	`conf`	An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo Vision. ReConFig Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri
2018	Misc	`conf`	Discussion on High Level Synthesis FPGA Design of Camera Calibration. CISIS Kazuya Uetsuhara, Hiroki Nagayama, Yuichiro Shibata, Kiyoshi Oguri
2018	J	`jnl`	FPGA Implementation of a Real-Time Super-Resolution System Using Flips and an RNS-Based CNN. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri
2017	J	`jnl`	Comparative Evaluation of FPGA Implementation Alternatives for Real-Time Robust Ellipse Estimation based on RANSAC Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Theint Theint Thu, Jimpei Hamamura, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri
2017	J	`jnl`	Deep-pipelined FPGA Implementation of Real-time Object Tracking using a Particle Filter. Int. J. Netw. Comput. Theint Theint Thu, Yoshiki Hayashida, Akane Tahara, Yuichiro Shibata, Kiyoshi Oguri
2017	—	`conf`	FPGA Implementation of A Graph Cut Algorithm For Stereo Vision. HEART Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri
2017	—	`conf`	FPGA implementation of a real-time super-resolution system with a CNN based on a residue number system. FPT Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri
2017	Misc	`conf`	HLS-Based FPGA Acceleration of Building-Cube Stencil Computation. CISIS Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri
2017	Misc	`conf`	Power Performance Analysis of FPGA-Based Particle Filtering for Realtime Object Tracking. CISIS Akane Tahara, Yoshiki Hayashida, Theint Theint Thu, Yuichiro Shibata, Kiyoshi Oguri
2016	—	`conf`	A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human Detection. ARC Masahito Oishi, Yoshiki Hayashida, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri
2016	—	`conf`	FPGA implementation of a real-time super-resolution system using a convolutional neural network. FPT Taito Manabe, Yuichiro Shibata, Kiyoshi Oguri
2016	—	`conf`	FPGA-based Real-Time Object Tracking Using a Particle Filter with Stream Architecture. CANDAR Akane Tahara, Yoshiki Hayashida, Theint Theint Thu, Yuichiro Shibata, Kiyoshi Oguri
2015	—	`conf`	An energy-efficient FPGA-based soft-core processor with a configurable word size ECC arithmetic accelerator. COOL Chips Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa
2015	J	`jnl`	Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration. IEICE Trans. Inf. Syst. Keisuke Dohi, Koji Okina, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri
2015	J	`jnl`	Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization. SIGARCH Comput. Archit. News Koji Okina, Rie Soejima, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri
2015	—	`conf`	Study of mirror box therapy support system by leap motion. ICCE-TW Makoto Fujimura, Shuhei Sato, Toshio Higashi, Kiyoshi Oguri
2014	J	`jnl`	A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis. SIGARCH Comput. Archit. News Rie Soejima, Koji Okina, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri
2014	B	`conf`	A soft-core processor for finite field arithmetic with a variable word size accelerator. FPL Aiko Iwasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa
2014	—	`conf`	FPGA Implementation of a Video Based Abnormal Action Detection System with Real-Time Cubic Higher Order Local Auto-Correlation Analysis. ARC Kaoru Hamasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri
2013	—	`conf`	A Fast Runtime Visualization of a GPU-Based 3D-FDTD Electromagnetic Simulation. CANDAR Kota Aoki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto
2013	J	`jnl`	FPGA Implementation of Human Detection by HOG Features with AdaBoost. IEICE Trans. Inf. Syst. Keisuke Dohi, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri
2013	—	`conf`	Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator. ReConFig Keisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri
2012	B	`conf`	Deep-pipelined FPGA implementation of ellipse estimation for eye tracking. FPL Keisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri
2012	J	`jnl`	Implementation of a GPU-Oriented Absorbing Boundary Condition for 3D-FDTD Electromagnetic Simulation. IEICE Trans. Inf. Syst. Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto
2012	J	`jnl`	Performance comparison of GPU programming frameworks with the striped Smith-Waterman algorithm. SIGARCH Comput. Archit. News Takeshi Kakimoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri
2011	J	`jnl`	A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU. SIGARCH Comput. Archit. News Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri
2011	—	`conf`	Clustering Documents with Maximal Substrings. ICEIS Tomonari Masada, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri
2011	—	`conf`	Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm. FPT Kazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri
2011	—	`conf`	Documents as a Bag of Maximal Substrings - An Unsupervised Feature Extraction for Document Clustering. ICEIS (1) Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri
2011	J	`jnl`	GPU implementation and optimization of electromagnetic simulation using the FDTD method for antenna designing. SIGARCH Comput. Archit. News Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto
2011	B	`conf`	Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation. FPL Keisuke Dohi, Yuji Yorita, Yuichiro Shibata, Kiyoshi Oguri
2011	—	`conf`	Semi-supervised Bibliographic Element Segmentation with Latent Permutations. ICADL Tomonari Masada, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri
2011	—	`conf`	Steering Time-Dependent Estimation of Posteriors with Hyperparameter Indexing in Bayesian Topic Models. PAKDD (1) Tomonari Masada, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri
2010	—	`conf`	A datapath classification method for FPGA-based scientific application accelerator systems. FPT Yui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri
2010	J	`jnl`	Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator. IPSJ Trans. Syst. LSI Des. Methodol. Hideki Yamada, Yui Ogawa, Tomonori Ooya, Tomoya Ishimori, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri
2010	J	`jnl`	Implementation of a programming environment with a multithread model for reconfigurable systems. SIGARCH Comput. Archit. News Keisuke Dohi, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri, Duncan A. Buell
2010	—	`conf`	Infinite latent process decomposition. BIBM Workshops Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri
2010	—	`conf`	Modeling Topical Trends over Continuous Time with Priors. ISNN (2) Tomonari Masada, Daiji Fukagawa, Atsuhiro Takasu, Yuichiro Shibata, Kiyoshi Oguri
2010	—	`conf`	Unsupervised Segmentation of Bibliographic Elements with Latent Permutations. WISE Workshops Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri
2009	—	`conf`	A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA. ReConFig Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri
2009	J	`jnl`	A novel multiple-walk parallel algorithm for the Barnes-Hut treecode on GPUs - towards cost effective, high performance N-body simulation. Comput. Sci. Res. Dev. Tsuyoshi Hamada, Keigo Nitadori, Khaled Benkrid, Yousuke Ohno, Gentaro Morimoto, Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri, Makoto Taiji
2009	C	`conf`	Accelerating Collapsed Variational Bayesian Inference for Latent Dirichlet Allocation with Nvidia CUDA Compatible Devices. IEA/AIE Tomonari Masada, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri
2009	—	`conf`	Accelerating Phase Correlation Functions Using GPU and FPGA. AHS Kentaro Matsuo, Tsuyoshi Hamada, Masayuki Miyoshi, Yuichiro Shibata, Kiyoshi Oguri
2009	—	`conf`	Bag of Timestamps: A Simple and Efficient Bayesian Chronological Mining. APWeb/WAIM Tomonari Masada, Atsuhiro Takasu, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri
2009	C	`conf`	Bayesian Multi-topic Microarray Analysis with Hyperparameter Reestimation. ADMA Tomonari Masada, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri
2009	B	`conf`	Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. FPL Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano
2009	A	`conf`	Dynamic hyperparameter optimization for bayesian topical trend analysis. CIKM Tomonari Masada, Daiji Fukagawa, Atsuhiro Takasu, Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri
2009	—	`conf`	Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator. ARC Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri
2008	B	`conf`	An optimization method of DMA transfer for a general purpose reconfigurable machine. FPL Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
2008	A	`conf`	Retrieving 3-d information with FPGA-based stream processing. FPGA Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri
2007	B	`conf`	A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. FPL Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
2007	J	`jnl`	An optimization method focusing on fixed-point arithmetic in applications for dynamically reconfigurable processor. Syst. Comput. Jpn. Miwa Miyata, Yuichiro Shibata, Kiyoshi Oguri
2007	—	`conf`	FPGA Implementation of a Statically Reconfigurable Java Environment for Embedded Systems. FPT Shinsuke Nino, Takayuki Mori, Younghun Ko, Yuichiro Shibata, Kiyoshi Oguri
2007	B	`conf`	Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine. FPL Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
2006	B	`conf`	An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor. FPL Miwa Miyata, Hideyuki Tsuchiya, Yuichiro Shibata, Kiyoshi Oguri
2005	B	`conf`	Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. FPL Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
2005	C	`conf`	Evaluation of Space Allocation Circuits. EUC Shinya Kyusaka, Hayato Higuchi, Taichi Nagamoto, Yuichiro Shibata, Kiyoshi Oguri
2005	C	`conf`	New Area Management Method Based on "Pressure" for Plastic Cell Architecture. EUC Taichi Nagamoto, Satoshi Yano, Mitsuru Uchida, Yuichiro Shibata, Kiyoshi Oguri
2004	B	`conf`	Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA. FPL Takehiro Ito, Yuichiro Shibata, Kiyoshi Oguri
2003	—	`conf`	Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. Asia-Pacific Computer Systems Architecture Conference Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya
2002	J	`jnl`	A Method of Mapping Finite State Machine into PCA Plastic Parts. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Minoru Inamori, Hiroshi Nakada, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri
2001	—	`conf`	PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. ASYNC Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri
2001	—	`conf`	Self-reorganising systems on VLSI circuits. ISCAS (4) Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig
2000	B	`conf`	An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. FPL Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada
2000	—	`conf`	Communicating logic: an alternative embedded stream processing paradigm. ASP-DAC Norbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada
1999	—	`conf`	Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer. IPPS/SPDP Workshops Hiroshi Nakada, Kiyoshi Oguri, Norbert Imlig, Minoru Inamori, Ryusuke Konishi, Hideyuki Ito, Kouichi Nagami, Tsunemichi Shiozawa
1998	B	`conf`	A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture. FPL Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Ryusuke Konishi, Norbert Imlig
1998	—	`conf`	General-Purpose Computer Architecture Based on Fully Programmable Logic. ICES Kiyoshi Oguri, Norbert Imlig, Hideyuki Ito, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa
1998	J	`jnl`	Message routing latency-minimizing method in an ASIC design for distributed cooperative communication protocol processing. Syst. Comput. Jpn. Hiroyuki Yamashita, Toshihiko Suguri, Shingo Kinoshita, Yasushi Okada, Kiyoshi Oguri
1998	Misc	`conf`	Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose. FCCM Kouichi Nagami, Kiyoshi Oguri, Tsunemichi Shiozawa, Hideyuki Ito, Ryusuke Konishi
1998	C	`conf`	The Plastic Cell Architecture for Dynamic Reconfigurable Computing. International Workshop on Rapid System Prototyping Hideyuki Ito, Kiyoshi Oguri, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa
1995	J	`jnl`	Test Synthesis from Behavioral Description Based on Data Transfer Analysis. IEICE Trans. Inf. Syst. Mitsuteru Yukishita, Kiyoshi Oguri, Tsukasa Kawaoka
1990	A	`conf`	Multi-Level Optimization for Large Scale ASICS. ICCAD Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura
1990	C	`conf`	Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer. ICCD Hiroshi Nakada, Naoya Sakurai, Yukiharu Kanayama, Naohisa Ohta, Kiyoshi Oguri