Kiyoshi Ishii

15 papers C 1Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2015 — conf
Analysis of propagation-delays in high-speed bipolar gates.
ISPACS
Yasushi Takahashi, Keisuke Eguchi, Akinobu Itoh, Kiyoshi Ishii
2012 — conf
Circuit technique for improving propagation delay times in CMOS source-coupled logic circuits.
ISPACS
Yuki Hagita, Kiyoshi Ishii
2008 J jnl
Estimation of Optimum Ion Energy for the Reduction of Resistivity in Bias Sputtering of ITO Thin Films.
IEICE Trans. Electron.
Kiyoshi Ishii, Yoshifumi Saitou, Kengo Furutani, Hiroshi Sakuma, Yoshito Ikeda
2008 J jnl
Special Section on Functional Thin Films for Optical Applications.
IEICE Trans. Electron.
Kiyoshi Ishii
2007 J jnl
Adaptive partial median filter for early CT signs of acute cerebral infarction.
Int. J. Comput. Assist. Radiol. Surg.
Yongbum Lee, Noriyuki Takahashi, Du-Yih Tsai, Kiyoshi Ishii
2005 J jnl
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki
2004 J jnl
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.
IEEE J. Solid State Circuits
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi
2004 — conf
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop].
ESSCIRC
Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata
2003 J jnl
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator.
IEEE J. Solid State Circuits
Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata
2002 J jnl
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX.
IEEE J. Solid State Circuits
Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino
2002 J jnl
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki
2000 C conf
A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit.
ISCAS
Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino
1995 J jnl
Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi
1994 J jnl
High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi
1994 J jnl
Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi