Kiyoo Itoh - RankMe

50 papers A 3C 2Journal 31Unranked 12

Year	Rank	Type	Title / Venue / Authors
2012	J	`jnl`	0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. IEICE Trans. Electron. Akira Kotabe, Kiyoo Itoh, Riichiro Takemura
2012	J	`jnl`	A Low- IEICE Trans. Electron. Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh
2012	J	`jnl`	Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. IEICE Trans. Electron. Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh
2011	—	`conf`	Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul
2011	—	`conf`	Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi
2011	J	`jnl`	Embedded Memories: Progress and a Look into the Future. IEEE Des. Test Comput. Kiyoo Itoh
2011	—	`book`	Nanoscale Memory Repair Masashi Horiguchi, Kiyoo Itoh
2010	J	`jnl`	Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. IEICE Trans. Electron. Kiyoo Itoh, Masanao Yamaoka, Takashi Oshima
2010	—	`conf`	Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs. PATMOS Kiyoo Itoh
2009	—	`conf`	Adaptive circuits for the 0.5-V nanoscale CMOS era. ISSCC Kiyoo Itoh
2009	A	`conf`	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ISLPED Kiyoo Itoh
2009	—	`conf`	Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. ISSCC Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh
2008	J	`jnl`	Memory at VLSI Circuits Symposium. IEEE J. Solid State Circuits Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi
2007	J	`jnl`	Long-Retention-Time, High-Speed DRAM Array with 12- IEICE Trans. Electron. Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
2007	—	`conf`	Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. ICECS Kiyoo Itoh
2007	—	`conf`	Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. ICECS Kiyoo Itoh, Riichiro Takemura
2007	—	`conf`	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
2007	—	`conf`	Low-voltage limitations of memory-rich nano-scale CMOS LSIs. ESSCIRC Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka
2007	—	`book`	Ultra-Low Voltage Nano-Scale Memories Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka
2006	A	`conf`	A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V ISLPED Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi
2006	C	`conf`	Ultra-low voltage nano-scale embedded RAMs. ISCAS Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara
2004	—	`conf`	Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara
2004	—	`conf`	Reviews and future prospects of low-voltage embedded RAMs. CICC Kiyoo Itoh, Kenichi Osada, Takayda Kawahara
2003	J	`jnl`	Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh
2002	J	`jnl`	A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura
2002	A	`conf`	Low-voltage memories for power-aware systems. ISLPED Kiyoo Itoh
2002	—	`conf`	Trends in Ultralow-Voltage RAM Technology. PATMOS Kiyoo Itoh
2001	J	`jnl`	A multigigabit DRAM technology with 6F IEEE J. Solid State Circuits Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh
2001	C	`conf`	Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC Kiyoo Itoh, Hiroyuki Mizuno
1997	J	`jnl`	Limitations and challenges of multigigabit DRAM chip design. IEEE J. Solid State Circuits Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe
1995	J	`jnl`	Trends in low-power RAM circuit technologies. Proc. IEEE Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome
1994	J	`jnl`	Subthreshold-current reduction circuits for multi-gigabit DRAM's. IEEE J. Solid State Circuits Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1994	J	`jnl`	Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. IEEE J. Solid State Circuits Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
1993	J	`jnl`	A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. IEEE J. Solid State Circuits Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki
1993	J	`jnl`	Sub-1-V swing internal bus architecture for future low-power ULSIs. IEEE J. Solid State Circuits Yoshinobu Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, Masakazu Aoki
1993	J	`jnl`	Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's. IEEE J. Solid State Circuits Masashi Horiguchi, Takeshi Sakata, Kiyoo Itoh
1992	J	`jnl`	Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. IEEE J. Solid State Circuits Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh
1991	J	`jnl`	A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture. IEEE J. Solid State Circuits Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto
1991	J	`jnl`	A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. IEEE J. Solid State Circuits Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh
1991	J	`jnl`	A flexible redundancy technique for high-density DRAMs. IEEE J. Solid State Circuits Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh, Tetsuro Matsumoto
1991	J	`jnl`	An experimental 1.5-V 64-Mb DRAM. IEEE J. Solid State Circuits Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh
1991	J	`jnl`	Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. IEEE J. Solid State Circuits Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki
1990	J	`jnl`	A 23-ns 1-Mb BiCMOS DRAM. IEEE J. Solid State Circuits Goro Kitsukawa, Kazumasa Yanagisawa, Yutaka Kobayashi, Yoshitaka Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiki Kawajiri, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh
1990	J	`jnl`	A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. IEEE J. Solid State Circuits Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto
1990	J	`jnl`	Trends in megabit DRAM circuit design. IEEE J. Solid State Circuits Kiyoo Itoh
1989	J	`jnl`	A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. IEEE J. Solid State Circuits Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi
1989	J	`jnl`	A 1.5-V DRAM for battery-based applications. IEEE J. Solid State Circuits Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto
1989	J	`jnl`	Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. IEEE J. Solid State Circuits Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto
1989	J	`jnl`	New DRAM noise generation under half-V IEEE J. Solid State Circuits Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh
1989	J	`jnl`	Substrate current reduction techniques for BiCMOS DRAM. IEEE J. Solid State Circuits Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto