Kiyohiro Furutani

11 papers C 1Journal 10

Year	Rank	Type	Title / Venue / Authors
2005	J	`jnl`	Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. IEICE Trans. Electron. Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara
2004	J	`jnl`	A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. IEEE J. Solid State Circuits Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara
2000	J	`jnl`	A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE J. Solid State Circuits Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara
1996	J	`jnl`	A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. IEEE J. Solid State Circuits Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki
1995	J	`jnl`	An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. IEEE J. Solid State Circuits Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki
1994	J	`jnl`	An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM. IEEE J. Solid State Circuits Kiyohiro Furutani, Hiroshi Miyamoto, Yoshikazu Morooka, Makoto Suwa, Hideyuki Ozaki
1994	J	`jnl`	An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs. IEEE J. Solid State Circuits Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki
1993	J	`jnl`	A VLSI chip set for a large-scale parallel inference machine: PIM/m. IEEE J. Solid State Circuits Hirohisa Machida, Hideki Ando, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Yamashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Masayoshi Sakao, Masao Nakaya
1990	C	`conf`	A pipelined microprocessor for logic programming languages. ICCD Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, Kiyohiro Furutani
1990	J	`jnl`	A speed-enhanced DRAM array architecture with embedded ECC. IEEE J. Solid State Circuits Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima
1989	J	`jnl`	A built-in Hamming code ECC circuit for DRAMs. IEEE J. Solid State Circuits Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko