Kiyoharu Hamaguchi

34 papers A* 6A 1B 4Misc 1Journal 17Unranked 5
YearRankTypeTitle / Venue / Authors
2023 J jnl
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage.
IPSJ Trans. Syst. LSI Des. Methodol.
Kiyoharu Hamaguchi
2019 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kiyoharu Hamaguchi
2018 J jnl
Applying an SMT Solver to Coverage-Driven Design Verification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kiyoharu Hamaguchi
2018 — conf
Extracting hardware assertions including word-level relations over multiple clock cycles.
ISQED
Mami Miyamoto, Kiyoharu Hamaguchi
2018 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kiyoharu Hamaguchi
2017 J jnl
Coverage-Driven Design Verification Using a Diverse SAT Solver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yosuke Kakiuchi, Kiyoharu Hamaguchi
2011 J jnl
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts.
Inf. Media Technol.
Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi
2011 J jnl
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts.
IPSJ Trans. Syst. LSI Des. Methodol.
Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi
2010 J jnl
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic.
IPSJ Trans. Syst. LSI Des. Methodol.
Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2010 J jnl
Approximate Model Checking Using a Subset of First-order Logic.
Inf. Media Technol.
Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara
2010 J jnl
Approximate Model Checking Using a Subset of First-order Logic.
IPSJ Trans. Syst. LSI Des. Methodol.
Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara
2009 J jnl
Checker Generation of Assertions with Local Variables for Model Checking.
Inf. Media Technol.
Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2009 J jnl
Checker Generation of Assertions with Local Variables for Model Checking.
IPSJ Trans. Syst. LSI Des. Methodol.
Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2008 B conf
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic.
ATVA
Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2007 J jnl
Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2006 J jnl
Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition.
IEICE Trans. Inf. Syst.
Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2005 — conf
Automatic monitor generation from regular expression based specifications for module interface verification.
ISCAS (4)
Yosuke Kakiuchi, A. Kitajima, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2004 J jnl
Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions.
IEICE Trans. Inf. Syst.
Kiyoharu Hamaguchi
2004 B conf
Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas.
ATVA
Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2001 — conf
Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions.
HLDVT
Kiyoharu Hamaguchi
2000 Misc conf
Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction.
COCOON
Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2000 B conf
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs.
FMCAD
Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara
1997 J jnl
Another Look at LTL Model Checking.
Formal Methods Syst. Des.
Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi
1995 A conf
Efficient construction of binary moment diagrams for verifying arithmetic circuits.
ICCAD
Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima
1994 A* conf
Another Look at LTL Model Checking.
CAV
Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi
1993 B conf
The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams.
ISAAC
Seiichiro Tani, Kiyoharu Hamaguchi, Shuzo Yajima
1992 A* conf
Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic.
CAV
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
1992 J jnl
Infinity-Regular Temporal Logic and its Model Checking Problem.
Theor. Comput. Sci.
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
1991 A* conf
Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic.
CAV
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
1991 A* conf
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.
CAV
Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima
1990 A* conf
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity.
CAV
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
1990 — conf
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity.
CAV (DIMACS/AMS volume)
Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
1990 A* conf
Vectorized Model Checking for Computation Tree Logic.
CAV
Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi
1990 — conf
Vectorized Model Checking for Computation Tree Logic.
CAV (DIMACS/AMS volume)
Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi