Kirti Gupta

37 papers Journal 31Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Memristor-Aided Dynamic Positive Feedback Source Coupled Logic.
J. Circuits Syst. Comput.
Shikha Mouria, Neeta Pandey, Kirti Gupta
2026 J jnl
Novel Design Approach of Three-Input Logic Implementation in Positive Feedback Source Coupled Logic Style.
J. Circuits Syst. Comput.
Shikha Mouria, Kirti Gupta, Neeta Pandey
2025 J jnl
High-performance noise-tolerant DTMOS Domino Schmitt trigger logic gate design.
Integr.
Bhawanand Jha, Rajeshwari Pandey, Kirti Gupta
2024 J jnl
A Monolithic Cybersecurity Architecture for Power Electronic Systems.
CoRR
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
2024 J jnl
A Monolithic Cybersecurity Architecture for Power Electronic Systems.
IEEE Trans. Smart Grid
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
2024 J jnl
Delay-Aware Semantic Sampling in Power Electronic Systems.
CoRR
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
2024 J jnl
Delay-Aware Semantic Sampling in Power Electronic Systems.
IEEE Trans. Smart Grid
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi
2024 J jnl
Demonstration of denial of charging attack on electric vehicle charging infrastructure and its consequences.
Int. J. Crit. Infrastructure Prot.
Kirti Gupta, Bijaya Ketan Panigrahi, Anupam Joshi, Kolin Paul
2024 J jnl
Integrating LSTM and NLP techniques for essay generation.
Intell. Decis. Technol.
Aditi Chauhan, Yashika Kukkar, Preeti Nagrath, Kirti Gupta, D. Jude Hemanth
2023 J jnl
Impact Assessment of Data Integrity Attacks in MVDC Shipboard Power Systems.
CoRR
Kirti Gupta, Subham Sahoo, Bijaya Ketan Panigrahi, Charalambos Konstantinou
2023 J jnl
Memristor-Based Architectures for PFSCL Circuit Realizations.
Circuits Syst. Signal Process.
Shikha, Neeta Pandey, Kirti Gupta
2023 J jnl
Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell.
Microelectron. J.
Damyanti Singh, Neeta Pandey, Kirti Gupta
2022 J jnl
A novel read decoupled 8T1M nvSRAM cell for near threshold operation.
Microelectron. J.
Damyanti Singh, Kirti Gupta, Neeta Pandey
2022 — conf
Handwriting Generation and Synthesis using Recurrent Neural Networks.
ICCCNT
Aniket Kumar, Mehul Madaan, Shubham Kumar, Aniket Saha, Kirti Gupta
2022 J jnl
On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates.
Microprocess. Microsystems
Ranjana Sivaram, Kirti Gupta, Neeta Pandey
2022 — conf
Test Suites Generation using UML Modelling and Heuristic Techniques: A Systematic Study.
ICIMMI
Kirti Gupta, Parul Goyal
2021 J jnl
A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region.
Int. J. Circuit Theory Appl.
Monica Gupta, Kirti Gupta, Neeta Pandey
2021 J jnl
A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region.
Int. J. Circuit Theory Appl.
Monica Gupta, Kirti Gupta, Neeta Pandey
2021 J jnl
Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm.
Microprocess. Microsystems
Monica Gupta, Kirti Gupta, Neeta Pandey
2021 J jnl
Was the Update of the 2015 Business Review Letter to the IEEE Justified?
IEEE Commun. Stand. Mag.
Georgios Effraimidis, Kirti Gupta, Urka Petrovcic
2020 J jnl
A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability.
Microelectron. J.
Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey
2020 J jnl
A new realization scheme for dynamic PFSCL style.
Integr.
Ranjana Sivaram, Kirti Gupta, Neeta Pandey
2020 — book
Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended
Kirti Gupta, Neeta Pandey, Maneesha Gupta
2019 J jnl
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shourya Gupta, Kirti Gupta, Benton H. Calhoun, Neeta Pandey
2018 — conf
MCML Dynamic Register Design.
MWSCAS
Neeta Pandey, Kirti Gupta, Bharat Choudhary
2018 J jnl
Pentavariate V
IEEE Trans. Circuits Syst. I Regul. Pap.
Shourya Gupta, Kirti Gupta, Neeta Pandey
2017 J jnl
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist.
IEEE Trans. Very Large Scale Integr. Syst.
Shourya Gupta, Kirti Gupta, Neeta Pandey
2017 — conf
Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies.
ICCSA (6)
Naman Saxena, Shruti Dutta, Neeta Pandey, Kirti Gupta
2017 J jnl
New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies.
J. Circuits Syst. Comput.
Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal
2017 J jnl
On Improving the Performance of Dynamic DCVSL Circuits.
J. Electr. Comput. Eng.
Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda
2016 — conf
A Novel Bulk Drain Connected 6T SRAM Cell.
ICACDS
Shobhit Kareer, Anchit Kumar, Kirti Gupta, Neeta Pandey
2016 J jnl
MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells.
Microelectron. J.
Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary
2016 J jnl
New Proposal for MCML Based Three-Input Logic Implementation.
VLSI Design
Neeta Pandey, Kirti Gupta, Bharat Choudhary
2015 J jnl
Multi-resolution wavelet-based image fusion for iris recognition.
Int. J. Appl. Pattern Recognit.
Kirti Gupta, Rashmi Gupta
2014 J jnl
An efficient triple-tail cell based PFSCL D latch.
Microelectron. J.
Neeta Pandey, Kirti Gupta, Maneesha Gupta
2013 J jnl
Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells.
Microelectron. J.
Kirti Gupta, Neeta Pandey, Maneesha Gupta
2011 J jnl
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic.
J. Electr. Comput. Eng.
Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta