King Ho Tam

11 papers A* 3A 3Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2015 A* conf
Criticality-dependency-aware timing characterization and analysis.
DAC
Yu-Ming Yang, King Ho Tam, Iris Hui-Ru Jiang
2014 A conf
Design and manufacturing process co-optimization in nano-technology.
ICCAD
Meng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin, Keny Tzu-Hen Lin, King Ho Tam, Ken Chung-Hsing Wang
2008 A* conf
Challenges in gate level modeling for delay and SI at 65nm and below.
DAC
Igor Keller, King Ho Tam, Vinod Kariat
2008 J jnl
Dual-V
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang
2007 — conf
Fast dual-vdd buffering based on interconnect prediction and sampling.
SLIP
Yu Hu, King Ho Tam, Tong Jing, Lei He
2007 J jnl
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2005 A conf
Buffer Insertion Considering Process Variation.
DATE
Jinjun Xiong, King Ho Tam, Lei He
2005 A* conf
Power optimal dual-Vdd buffered tree considering buffer stations and blockages.
DAC
King Ho Tam, Lei He
2005 A conf
Power-optimal repeater insertion considering Vdd and Vth as design freedoms.
ISLPED
Yu Ching Chang, King Ho Tam, Lei He
2005 — conf
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.
ISPD
Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2004 — conf
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.
ISQED
Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He