Kimiyoshi Usami

86 papers A* 3A 6B 2C 3Misc 1Journal 26Unranked 44

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation. NorCAS Kimiyoshi Usami, Mina Fukushima, Songxiang Wang, Kaito Nagai
2024	J	`jnl`	Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. IEEE Trans. Very Large Scale Integr. Syst. Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho
2023	—	`conf`	A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered by Energy Harvesters with Ultra-Low Output Voltage. IoTaIS Kimiyoshi Usami, Songxiang Wang, Kaito Nagai, Giovanna Latronico, Paolo Mele
2023	—	`conf`	A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing. VLSI Technology and Circuits Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi
2023	J	`jnl`	A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
2022	—	`conf`	Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations. NorCAS Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano
2021	J	`jnl`	Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM. IEICE Trans. Electron. Yoshinori Ono, Kimiyoshi Usami
2021	—	`conf`	Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. MCSoC Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
2020	—	`conf`	Energy Efficient Approximate Storing of Image Data for MTJ Based Non-volatile Memory. NVMSA Yoshinori Ono, Kimiyoshi Usami
2020	—	`conf`	Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. COOL CHIPS Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda
2018	—	`conf`	A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. ReConFig Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
2018	—	`conf`	Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. NVMSA Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
2017	—	`conf`	Building block multi-chip systems using inductive coupling through chip interface. ISOCC Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
2017	—	`conf`	Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. ISOCC Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano
2017	J	`jnl`	Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation in Silicon-on-Thin-BOX (SOTB). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yusuke Yoshida, Kimiyoshi Usami
2017	—	`conf`	Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI. VLSI-SoC (Selected Papers) Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano
2017	C	`conf`	Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. VLSI-SoC Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano
2017	—	`conf`	Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. NVMSA Masaru Kudo, Kimiyoshi Usami
2017	J	`jnl`	Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. IEEE Trans. Very Large Scale Integr. Syst. Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2016	J	`jnl`	An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
2016	J	`jnl`	Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2015	J	`jnl`	A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki
2015	J	`jnl`	A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2015	—	`conf`	A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. COOL Chips Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano
2015	J	`jnl`	An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2015	A	`conf`	An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. ISLPED Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2014	—	`conf`	A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
2014	—	`conf`	A Thermal Management System for Building Block Computing Systems. MCSoC Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2014	—	`conf`	A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2014	—	`conf`	Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2014	A	`conf`	Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura
2014	—	`conf`	Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2013	J	`jnl`	A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	B	`conf`	Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	J	`jnl`	Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki
2013	J	`jnl`	Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kimiyoshi Usami
2012	—	`conf`	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2012	B	`conf`	CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	—	`conf`	Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	—	`conf`	Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
2012	—	`conf`	Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2012	—	`ch.`	Geyser. Handbook of Energy-Aware and Green Computing Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura
2012	—	`conf`	Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
2012	—	`conf`	Trade-off analysis of fine-grained power gating methods for functional units in a CPU. COOL Chips Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano
2011	—	`conf`	Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011	J	`jnl`	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
2011	J	`jnl`	Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011	J	`jnl`	Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011	—	`conf`	Dynamic V ARC Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami
2011	—	`conf`	Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
2011	A	`conf`	On-chip detection methodology for break-even time of power gated function units. ISLPED Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
2011	J	`jnl`	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2011	—	`conf`	SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo
2011	J	`jnl`	Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami
2010	—	`conf`	Adaptive power gating for function units in a microprocessor. ISQED Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2010	—	`conf`	Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo
2010	—	`conf`	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2009	—	`conf`	Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano
2009	Misc	`conf`	Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
2008	C	`conf`	A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2008	—	`conf`	Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano
2008	A	`conf`	Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. DATE Jerry Frenkil, Ken Choi, Kimiyoshi Usami
2007	—	`conf`	Overview on Low Power SoC Design Technology. ASP-DAC Kimiyoshi Usami
2006	C	`conf`	A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. ICCD Kimiyoshi Usami, Naoaki Ohkubo
2006	J	`jnl`	Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naoaki Ohkubo, Kimiyoshi Usami
2006	—	`conf`	Delay modeling and static timing analysis for MTCMOS circuits. ASP-DAC Naoaki Ohkubo, Kimiyoshi Usami
2002	A	`conf`	Automated selective multi-threshold design for ultra-low standby applications. ISLPED Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
2002	J	`jnl`	Code Coverage-Based Power Estimation Techniques for Microprocessors. J. Circuits Syst. Comput. Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
2002	J	`jnl`	Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
2000	A*	`conf`	Function-level power estimation methodology for microprocessors. DAC Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
2000	—	`conf`	Low-power design methodology and applications utilizing dual supply voltages. ASP-DAC Kimiyoshi Usami, Mutsunori Igarashi
2000	—	`conf`	Low-power technique for on-chip memory using biased partitioning and access concentration. CICC Naoyuki Kawabe, Kimiyoshi Usami
1998	J	`jnl`	A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama
1998	—	`conf`	A Clock-Gating Method for Low-Power LSI Design. ASP-DAC Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi
1998	—	`conf`	A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. CICC Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda
1998	J	`jnl`	Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE J. Solid State Circuits Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa, Makoto Ichida, Kazutaka Nogami
1998	A*	`conf`	Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda
1997	A	`conf`	A low-power design method using multiple supply voltages. ISLPED Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka
1995	—	`conf`	Clustered voltage scaling technique for low-power design. ISLPD Kimiyoshi Usami, Mark Horowitz
1991	J	`jnl`	Hierarchical symbolic design methodology for large-scale data paths. IEEE J. Solid State Circuits Kimiyoshi Usami, Yukio Sugeno, Nobu Matsumoto, Shojiro Mori
1990	A*	`conf`	Datapath Generator Based on Gate-Level Symbolic Layout. DAC Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori
1989	J	`jnl`	Design of a 32 bit microprocessor, TX1. IEEE J. Solid State Circuits Takeji Tokumaru, Eeji Masuda, Chikahiro Hori, Kimiyoshi Usami, Misao Miyata, Jun Iwamura