Kimia Zamiri Azar

65 papers A* 2A 9B 2C 2Misc 2Journal 35Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation. CoRR M. Zafir Sadik Khan, Kimia Zamiri Azar, Hadi Mardani Kamali
2026	J	`jnl`	MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code Generation. CoRR Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar
2026	J	`jnl`	NuRedact: Non-Uniform eFPGA Architecture for Low-Overhead and Secure IP Redaction. CoRR Voktho Das, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	C	`conf`	CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage. ICCD Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar
2025	J	`jnl`	CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage. CoRR Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar
2025	A	`conf`	DecoRTL: A Run-Time Decoding Framework for RTL Code Generation with LLMs. ICCAD Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	J	`jnl`	DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs. CoRR Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	Misc	`conf`	LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware. VTS Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar
2025	J	`jnl`	LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware. CoRR Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar
2025	J	`jnl`	RTL++: Graph-enhanced LLM for RTL Code Generation. CoRR Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	J	`jnl`	Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification. IEEE Trans. Very Large Scale Integr. Syst. Hasan Al Shaikh, Shuvagata Saha, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, Fahim Rahman
2025	J	`jnl`	Rethinking SoC Verification for Secure Cross-Layer Interactions. IEEE Des. Test Hasan Al Shaikh, Shuvagata Saha, Sujan Kumar Saha, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor
2025	C	`conf`	SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation. ICCD M. Zafir Sadik Khan, Nowfel Mashnoor, Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	J	`jnl`	SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation. CoRR M. Zafir Sadik Khan, Nowfel Mashnoor, Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	J	`jnl`	SOAR: Secure Once, Adapt at Runtime With eFPGA-Based Redaction for IP Protection. IEEE Access Voktho Das, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	J	`jnl`	StepGrade: Grading Programming Assignments with Context-Aware LLMs. CoRR Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali
2025	—	`conf`	TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization. COINS Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar
2025	J	`jnl`	TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization. CoRR Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar
2024	J	`jnl`	Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration. IEEE Access Md Sami Ul Islam Sami, Tao Zhang, Amit Mazumder Shuvo, Md. Saad Ul Haque, Paul E. Calzada, Kimia Zamiri Azar, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark Mohammad Tehranipoor
2024	J	`jnl`	Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions. IEEE Des. Test Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Mark Tehranipoor, Farimah Farahmandi
2024	B	`conf`	FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection. ASPDAC Nusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor
2024	J	`jnl`	Fuzzing for Automated SoC Security Verification: Challenges and Solution. IEEE Des. Test Muhammad Monir Hossain, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
2024	A*	`conf`	GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package. DAC Galib Ibne Haidar, Kimia Zamiri Azar, Hadi Mardani Kamali, Mark Tehranipoor, Farimah Farahmandi
2024	—	`conf`	HI-SST: Safeguarding SiP Authenticity Through Secure Split-Test in Heterogeneous Integration. ISVLSI Paul E. Calzada, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor
2024	J	`jnl`	Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM. ACM Trans. Design Autom. Electr. Syst. Paul E. Calzada, Md Sami Ul Islam Sami, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
2024	J	`jnl`	Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration. IEEE Trans. Inf. Forensics Secur. Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
2024	A	`conf`	RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation. DATE Nurun Nahar Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor
2024	A	`conf`	SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits. ITC Galib Ibne Haidar, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Mark Tehranipoor, Farimah Farahmandi
2024	—	`conf`	SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation. ACM Great Lakes Symposium on VLSI Bulbul Ahmed, M. Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Fahim Rahman, Mark Tehranipoor
2024	J	`jnl`	SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation. IEEE Trans. Very Large Scale Integr. Syst. Tao Zhang, Md Latifur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi
2024	J	`jnl`	The Road Not Taken: eFPGA Accelerators Utilized for SoC Security Auditing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Mark Tehranipoor, Farimah Farahmandi
2023	—	`conf`	EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators. DFT Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi
2023	—	`conf`	Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking. ACM Great Lakes Symposium on VLSI Mohammad Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Hadi Mardani Kamali
2023	B	`conf`	PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates. ETS Upoma Das, M. Sazadur Rahman, N. Nalla Anandakumar, Kimia Zamiri Azar, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi
2023	—	`conf`	QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy. DFT Hasan Al Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, Fahim Rahman
2023	—	`conf`	SHarPen: SoC Security Verification by Hardware Penetration Test. ASP-DAC Hasan Al Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
2023	A	`conf`	SheLL: Shrinking eFPGA Fabrics for Logic Locking. DATE Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor
2023	A	`conf`	SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing. DATE Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
2023	A	`conf`	TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing. ICCAD Muhammad Monir Hossain, Nusrat Farzana Dipu, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
2022	J	`jnl`	Advances in Logic Locking: Past, Present, and Prospects. IACR Cryptol. ePrint Arch. Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor
2022	J	`jnl`	Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions. IACR Cryptol. ePrint Arch. Kimia Zamiri Azar, Muhammad Monir Hossain, Arash Vafaei, Hasan Al Shaikh, Nurun N. Mondol, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi
2022	—	`conf`	Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers. HOST Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
2021	—	`conf`	ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing. ISQED Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2021	J	`jnl`	Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. IEEE Trans. Very Large Scale Integr. Syst. Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan
2021	J	`jnl`	From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains. IEEE Access Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan
2020	Misc	`conf`	DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain. VTS Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan
2020	J	`jnl`	DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain. CoRR Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan
2020	J	`jnl`	ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things. CoRR Hadi Mardani Kamali, Kimia Zamiri Azar, Shervin Roshanisefat, Ashkan Vakil, Avesta Sasan
2020	A	`conf`	InterLock: An Intercorrelated Logic and Routing Locking. ICCAD Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2020	J	`jnl`	InterLock: An Intercorrelated Logic and Routing Locking. CoRR Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2020	A	`conf`	NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures. ICCAD Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan
2020	J	`jnl`	NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures. CoRR Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan
2020	—	`conf`	On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. ACM Great Lakes Symposium on VLSI Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2020	J	`jnl`	On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic. CoRR Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2020	—	`conf`	SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. ISVLSI Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2020	J	`jnl`	SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption. CoRR Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2019	A	`conf`	COMA: Communication and Obfuscation Management Architecture. RAID Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan
2019	J	`jnl`	COMA: Communication and Obfuscation Management Architecture. CoRR Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan
2019	A*	`conf`	Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks. DAC Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan
2019	J	`jnl`	SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan
2019	—	`conf`	Threats on Logic Locking: A Decade Later. ACM Great Lakes Symposium on VLSI Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan
2019	J	`jnl`	Threats on Logic Locking: A Decade Later. CoRR Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan
2018	J	`jnl`	DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture. IEEE Trans. Computers Hadi Mardani Kamali, Kimia Zamiri Azar, Shaahin Hessabi
2018	—	`conf`	LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. ISVLSI Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan
2018	J	`jnl`	LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection. CoRR Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan