Kia Bazargan - RankMe

104 papers A* 4A 31B 5C 8Misc 5Journal 32Unranked 17

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Compressing Neural Networks using Learnable 1D Non-Linear Functions. ACM Trans. Reconfigurable Technol. Syst. Gaurav Singh, Kia Bazargan
2025	A	`conf`	TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees. FPGA Alireza Khataei, Kia Bazargan
2025	J	`jnl`	TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees. CoRR Alireza Khataei, Kia Bazargan
2024	A	`conf`	CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond. FPGA Alireza Khataei, Kia Bazargan
2024	J	`jnl`	SimBU: Self-Similarity-Based Hybrid Binary-Unary Computing for Nonlinear Functions. IEEE Trans. Computers Alireza Khataei, Gaurav Singh, Kia Bazargan
2023	A	`conf`	Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing. FPGA Alireza Khataei, Gaurav Singh, Kia Bazargan
2023	A	`conf`	Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing. ICCAD Alireza Khataei, Kia Bazargan
2023	Misc	`conf`	Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures. FCCM Alireza Khataei, Gaurav Singh, Kia Bazargan
2022	J	`jnl`	Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs. ACM Trans. Reconfigurable Technol. Syst. S. Rasoul Faraji, Pierre Abillama, Kia Bazargan
2020	J	`jnl`	Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel. IEEE Trans. Very Large Scale Integr. Syst. Zhiheng Wang, Devan Larso, Morgen Barker, Soheil Mohajer, Kia Bazargan
2020	C	`conf`	Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing. ISCAS M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja
2020	C	`conf`	HBUCNNA: Hybrid Binary-Unary Convolutional Neural Network Accelerator. ISCAS S. Rasoul Faraji, Pierre Abillama, Gaurav Singh, Kia Bazargan
2020	J	`jnl`	Hybrid Binary-Unary Hardware Accelerator. IEEE Trans. Computers S. Rasoul Faraji, Kia Bazargan
2020	A	`conf`	Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs. ICCAD S. Rasoul Faraji, Kia Bazargan
2020	Misc	`conf`	Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications. FCCM S. Rasoul Faraji, Pierre Abillama, Kia Bazargan
2020	J	`jnl`	Parallel Unary Computing Based on Function Derivatives. ACM Trans. Reconfigurable Technol. Syst. Soheil Mohajer, Zhiheng Wang, Kia Bazargan, Yuyang Li
2019	—	`conf`	Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. ISQED M. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J. Lilja, Kia Bazargan
2019	A	`conf`	Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing. DATE S. Rasoul Faraji, M. Hassan Najafi, Bingzhe Li, David J. Lilja, Kia Bazargan
2019	—	`conf`	Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing. ASAP M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja
2019	C	`conf`	HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA. ICCD Sayed Abdolrasouol Faraji, Gaurav Singh, Kia Bazargan
2019	—	`conf`	Hybrid binary-unary hardware accelerator. ASP-DAC S. Rasoul Faraji, Kia Bazargan
2019	A	`ed.`	Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019 FPGA Kia Bazargan, Stephen Neuendorffer
2018	—	`conf`	Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks. ASP-DAC Zhiheng Wang, Soheil Mohajer, Kia Bazargan
2018	J	`jnl`	Low-Cost Sorting Network Circuits Using Unary Processing. IEEE Trans. Very Large Scale Integr. Syst. M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
2018	A	`ed.`	Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018 FPGA Jason Helge Anderson, Kia Bazargan
2018	A	`conf`	Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data. FPGA Soheil Mohajer, Zhiheng Wang, Kia Bazargan
2017	J	`jnl`	A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing. ACM J. Emerg. Technol. Comput. Syst. M. Hassan Najafi, Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel
2017	—	`conf`	A memory optimized mersenne-twister random number generator. MWSCAS Naman Saraf, Kia Bazargan
2017	J	`jnl`	An Overview of Time-Based Computing with Stochastic Constructs. IEEE Micro M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
2017	J	`jnl`	Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits. IEEE Trans. Computers M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
2017	C	`conf`	Power and Area Efficient Sorting Networks Using Unary Processing. ICCD M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
2017	J	`jnl`	Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map. IEEE Trans. Very Large Scale Integr. Syst. Zhiheng Wang, Ryan N. Goh, Kia Bazargan, Arnd Scheel, Naman Saraf
2017	J	`jnl`	Time-Encoded Values for Highly Efficient Stochastic Circuits. IEEE Trans. Very Large Scale Integr. Syst. M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
2016	—	`conf`	Polynomial Arithmetic Using Sequential Stochastic Logic. ACM Great Lakes Symposium on VLSI Naman Saraf, Kia Bazargan
2016	—	`conf`	Polysynchronous stochastic circuits. ASP-DAC M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan
2016	A	`conf`	t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only). FPGA Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan
2015	J	`jnl`	Axilog: Abstractions for Approximate Hardware Design and Reuse. IEEE Micro Divya Mahajan, Kartik Ramkrishnan, Rudra Jariwala, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Anandhavel Nagendrakumar, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan
2015	A	`conf`	Axilog: language support for approximate hardware design. DATE Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan
2015	A*	`conf`	Randomness meets feedback: stochastic implementation of logistic map dynamical system. DAC Zhiheng Wang, Naman Saraf, Kia Bazargan, Arnd Scheel
2014	A	`conf`	Binary stochastic implementation of digital logic. FPGA Yanzi Zhu, Peiran Suo, Kia Bazargan
2014	J	`jnl`	Computation on Stochastic Bit Streams Digital Image Processing Case Studies. IEEE Trans. Very Large Scale Integr. Syst. Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel
2014	A	`conf`	IIR filters using stochastic arithmetic. DATE Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel
2014	J	`jnl`	Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines. IEEE Trans. Computers Peng Li, David J. Lilja, Weikang Qian, Marc D. Riedel, Kia Bazargan
2013	A	`conf`	Sequential logic to transform probabilities. ICCAD Naman Saraf, Kia Bazargan
2013	C	`conf`	Stochastic functions using sequential logic. ICCD Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel
2012	A	`conf`	An efficient implementation of numerical integration using logical computation on stochastic bit streams. ICCAD Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel
2012	—	`conf`	Case Studies of Logical Computation on Stochastic Bit Streams. PATMOS Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan, Marc D. Riedel
2012	A	`conf`	The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic. ICCAD Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel
2012	—	`conf`	The synthesis of linear Finite State Machine-based Stochastic Computational Elements. ASP-DAC Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja
2011	J	`jnl`	An Architecture for Fault-Tolerant Computation with Stochastic Logic. IEEE Trans. Computers Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja
2011	A	`conf`	FPGA placement by graph isomorphism (abstract only). FPGA Hossein Omidian Savarbaghi, Kia Bazargan
2010	—	`conf`	A fast SPFD-based rewiring technique. ASP-DAC Pongstorn Maidee, Kia Bazargan
2010	J	`jnl`	Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pongstorn Maidee, Kia Bazargan
2009	—	`conf`	A reconfigurable stochastic architecture for highly reliable computing. ACM Great Lakes Symposium on VLSI Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja
2009	—	`conf`	A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan
2009	—	`conf`	Estimation and optimization of reliability of noisy digital circuits. ISQED Satish Sivaswamy, Kia Bazargan, Marc D. Riedel
2009	J	`jnl`	Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan
2009	A	`conf`	The synthesis of combinational logic to generate probabilities. ICCAD Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja
2009	A	`conf`	Using randomization to cope with circuit uncertainty. DATE Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan
2008	—	`ch.`	FPGA Technology Mapping, Placement, and Routing. Handbook of Algorithms for Physical Design Automation Kia Bazargan
2008	B	`conf`	FPGA family composition and effects of specialized blocks. FPL Pongstorn Maidee, Nagib Hakim, Kia Bazargan
2008	—	`ch.`	Physical Design for Three-Dimensional Circuits. Handbook of Algorithms for Physical Design Automation Kia Bazargan, Sachin S. Sapatnekar
2008	J	`jnl`	Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Satish Sivaswamy, Kia Bazargan
2008	A	`conf`	Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. ICCAD Hushrav Mogal, Kia Bazargan
2007	B	`conf`	A generalized and unified SPFD-based rewiring technique. FPL Pongstorn Maidee, Kia Bazargan
2007	A	`conf`	Clustering based pruning for statistical criticality computation under process variations. ICCAD Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan
2007	J	`jnl`	Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kia Bazargan, André DeHon
2007	A	`conf`	Microarchitecture floorplanning for sub-threshold leakage reduction. DATE Hushrav Mogal, Kia Bazargan
2007	B	`conf`	Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. FPL Satish Sivaswamy, Kia Bazargan
2007	A	`conf`	Variation-aware routing for FPGAs. FPGA Satish Sivaswamy, Kia Bazargan
2006	B	`conf`	Defect-Tolerant FPGA Architecture Exploration. FPL Pongstorn Maidee, Kia Bazargan
2006	J	`jnl`	Non-contiguous linear placement for reconfigurable fabrics. Int. J. Embed. Syst. Cristinel Ababei, Kia Bazargan
2006	J	`jnl`	Statistical Analysis and Design of HARP FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
2006	J	`jnl`	Three-dimensional place and route for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
2005	A	`conf`	3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA Cristinel Ababei, Hushrav Mogal, Kia Bazargan
2005	J	`jnl`	A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. J. Comput. Sci. Technol. Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
2005	A	`conf`	HARP: hard-wired routing pattern FPGAs. FPGA Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh
2005	J	`jnl`	Placement and Routing in 3D Integrated Circuits. IEEE Des. Test Comput. Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar
2005	—	`conf`	Three-dimensional place and route for FPGAs. ASP-DAC Cristinel Ababei, Hushrav Mogal, Kia Bazargan
2005	J	`jnl`	Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
2004	J	`jnl`	Editorial: Special issue on dynamically adaptable embedded systems. ACM Trans. Embed. Comput. Syst. John C. Lach, Kia Bazargan
2004	—	`conf`	Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory. Asia-Pacific Computer Systems Architecture Conference Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
2004	B	`conf`	Exploring Potential Benefits of 3D FPGA Integration. FPL Cristinel Ababei, Pongstorn Maidee, Kia Bazargan
2004	A	`conf`	Non-Contiguous Linear Placement for Reconfigurable Fabrics. IPDPS Cristinel Ababei, Kia Bazargan
2003	A*	`conf`	Fast timing-driven partitioning-based placement for island style FPGAs. DAC Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
2003	C	`conf`	HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. DSD Karthikeyan Bhasyam, Kia Bazargan
2003	A	`conf`	Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. DATE Wonjoon Choi, Kia Bazargan
2003	A	`conf`	Incremental Placement for Timing Optimization. ICCAD Wonjoon Choi, Kia Bazargan
2003	Misc	`conf`	Linear Placement for Static / Dynamic Reconfiguration in JBits. FCCM Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan
2003	A	`conf`	Placement Method Targeting Predictability Robustness and Performance. ICCAD Cristinel Ababei, Kia Bazargan
2003	Misc	`conf`	Timing Minimization by Statistical Timing hMetis-based Partitioning. VLSI Design Cristinel Ababei, Kia Bazargan
2002	A*	`conf`	A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. DAC Jinghuan Chen, Jaekyun Moon, Kia Bazargan
2002	A	`conf`	Multi-objective circuit partitioning for cutsize and path-based delay minimization. ICCAD Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis
2002	A	`conf`	Statistical Timing Driven Partitioning for VLSI Circuits. DATE Cristinel Ababei, Kia Bazargan
2001	J	`jnl`	Fast floorplanning for effective prediction and construction. IEEE Trans. Very Large Scale Integr. Syst. Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
2001	A*	`conf`	Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. DAC Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
2000	J	`jnl`	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. Des. Autom. Embed. Syst. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
2000	Misc	`conf`	A C to Hardware/Software Compiler. FCCM Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh
2000	C	`conf`	Fast Hierarchical Floorplanning with Congestion and Timing Control. ICCD Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh
2000	J	`jnl`	Fast Template Placement for Reconfigurable Computing Systems. IEEE Des. Test Comput. Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
2000	—	`conf`	Fast and accurate estimation of floorplans in logic/high-level synthesis. ACM Great Lakes Symposium on VLSI Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
1999	C	`conf`	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. IEEE International Workshop on Rapid System Prototyping Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh
1999	J	`jnl`	Nostradamus: a floorplanner of uncertain designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kia Bazargan, Samjung Kim, Majid Sarrafzadeh
1998	—	`conf`	Nostradamus: a floorplanner of uncertain design. ISPD Kia Bazargan, Samjung Kim, Majid Sarrafzadeh