Ki Chul Chun

19 papers A 2C 1Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
Multi-Modal Explainable Deep Learning-Assisted Signal Integrity Prediction Methodology.
ICECS
Jiyoung Yoon, Taeryeong Kim, Ki Chul Chun, Jonghoon Kim, Seong-Ook Jung
2021 J jnl
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.
IEEE J. Solid State Circuits
Ki Chul Chun, Yong-Ki Kim, Yesin Ryu, Jaewon Park, Chi Sung Oh, Young-Yong Byun, So-Young Kim, Dong-Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung-Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Sooyoung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Jung-Bae Lee
2021 J jnl
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process.
IEEE Access
Jaewon Park, Jae Hoon Lee, Sang-Kil Park, Ki Chul Chun, Kyomin Sohn, Sungho Kang
2020 — conf
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.
ISSCC
Chi-Sung Oh, Ki Chul Chun, Young-Yong Byun, Yong-Ki Kim, So-Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sang-uhn Cha, Dong-Hak Shin, Jungyu Lee, Jong-Pil Son, Byung-Kyu Ho, Seong-Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yong-Sik Park, Kijun Lee, Myung-Kyu Lee, Seungduk Baek, Junyong Noh, Jae-Wook Lee, SeungSeob Lee, Sooyoung Kim, Bo-Tak Lim, Seouk-Kyu Choi, Jin-Guk Kim, Hye-In Choi, Hyuk-Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang-Il Park, Jung-Bae Lee
2018 — conf
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
ISSCC
Ki Chul Chun, Yonggyu Chu, Jin-Seok Heo, Tae-sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, Inkyu Moon, Young-Ju Kim, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung-Bum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang
2014 J jnl
A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications.
IEEE J. Solid State Circuits
Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2013 J jnl
A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme.
IEEE J. Solid State Circuits
Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2013 J jnl
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory.
IEEE J. Solid State Circuits
Ki Chul Chun, Hui Zhao, Jonathan D. Harms, Tony Tae-Hyoung Kim, Jianping Wang, Chris H. Kim
2013 J jnl
A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei Zhang, Ki Chul Chun, Chris H. Kim
2013 — conf
A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications.
CICC
Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2012 J jnl
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor.
IEEE J. Solid State Circuits
Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim
2012 J jnl
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches.
IEEE J. Solid State Circuits
Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim
2012 — conf
A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme.
VLSIC
Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2012 — conf
A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode.
CICC
Wei Zhang, Ki Chul Chun, Chris H. Kim
2011 J jnl
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches.
IEEE J. Solid State Circuits
Ki Chul Chun, Pulkit Jain, Jung-Hwa Lee, Chris H. Kim
2011 — conf
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies.
ISSCC
Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim
2010 C conf
Logic-compatible embedded DRAM design for memory intensive low power systems.
ISCAS
Ki Chul Chun, Pulkit Jain, Chris H. Kim
2010 A conf
Variation aware performance analysis of gain cell embedded DRAMs.
ISLPED
Wei Zhang, Ki Chul Chun, Chris H. Kim
2009 A conf
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.
ISLPED
Ki Chul Chun, Pulkit Jain, Chris H. Kim