Ki-Wook Kim

34 papers A* 4A 6B 1Journal 14Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
ScienceIoT: Evolution of the Wireless Infrastructure of KREONET.
Sensors
Cheonyong Kim, Joobum Kim, Ki-Hyeon Kim, Sang-Kwon Lee, Ki-Wook Kim, Syed Asif Raza Shah, Young-Hoon Goo
2018 J jnl
In-Network Data Processing in Software-Defined IoT with a Programmable Data Plane.
Mob. Inf. Syst.
Ki-Wook Kim, Sung-Gi Min, Youn-Hee Han
2017 — conf
A programmable data plane to support in-network data processing in software-defined IoT.
ICTC
Ki-Wook Kim, Sung-Gi Min, Youn-Hee Han
2017 J jnl
An Authentication and Key Management Mechanism for Resource Constrained Devices in IEEE 802.11-based IoT Access Networks.
Sensors
Ki-Wook Kim, Youn-Hee Han, Sung-Gi Min
2009 — conf
Distributed cluster head election algorithm using local energy estimation.
ICHIT
Ki-Wook Kim, Kwang-Ryoul Kim, Sung-Gi Min
2004 J jnl
Coupling-aware high-level interconnect synthesis [IC layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
2003 J jnl
Chip-level charged-device modeling and simulation in CMOS integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
2003 J jnl
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. Very Large Scale Integr. Syst.
Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
2003 J jnl
Energy-efficient skewed static logic with dual Vt: design and synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
2003 J jnl
Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst.
Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
2003 J jnl
Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
2003 J jnl
Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 A conf
Coupling-aware high-level interconnect synthesis for low power.
ICCAD
Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
2002 J jnl
Domino logic synthesis based on implication graph.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
2002 A conf
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.
DATE
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 J jnl
Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst.
Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
2002 A* conf
Low-swing clock domino logic incorporating dual supply and dual threshold voltages.
DAC
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 J jnl
Noise constrained transistor sizing and power optimization for dual Vs
IEEE Trans. Very Large Scale Integr. Syst.
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 — conf
Optimal Timing for Skew-Tolerant High-Speed Domino Logic.
ISVLSI
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2002 A* conf
VeriCDF: a new verification methodology for charged device failures.
DAC
Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang
2001 A* conf
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
DAC
Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
2001 — conf
Coupling-aware minimum delay optimization for domino logic circuits.
ISCAS (5)
Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang
2001 J jnl
Crosstalk noise minimization in domino logic design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ki-Wook Kim, Sung-Mo Kang
2001 — conf
Energy-efficient skewed static logic design with dual Vt.
ISCAS (4)
Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
2001 — conf
Noise constrained power optimization for dual VT domino logic.
ISCAS (4)
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2001 — —
Reliable Low -Power Solution for High -Performance VLSI Circuit Design
Ki-Wook Kim
2001 — conf
Skew-tolerant high-speed (STHS) domino logic.
ISCAS (4)
Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang
2001 — conf
Transistor sizing for reliable domino logic design in dual threshold voltage technologies.
ACM Great Lakes Symposium on VLSI
Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
2000 A conf
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
ICCAD
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang
2000 A* conf
Domino logic synthesis minimizing crosstalk.
DAC
Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang
2000 A conf
Noise-aware power optimization for on-chip interconnect.
ISLPED
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
1999 A conf
Implication graph based domino logic synthesis.
ICCAD
Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
1999 A conf
Logic Transformation for Low Power Synthesis.
DATE
Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
1996 B conf
VIRON: An Annotation-Based Video Information Retrieval System.
COMPSAC
Ki-Wook Kim, Ki-Byoung Kim, Hyoung-Joo Kim