Khosrow Hajsadeghi

22 papers C 2Journal 11Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
CLIP-Joint-Detect: End-to-End Joint Training of Object Detectors with Contrastive Vision-Language Supervision.
CoRR
Behnam Raoufi, Hossein Sharify, Mohamad Mahdee Ramezanee, Khosrow Hajsadeghi, Saeed Bagheri Shouraki
2025 J jnl
Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA.
Circuits Syst. Signal Process.
Abolfazl Roshanpanah, Pooya Torkzadeh, Khosrow Hajsadeghi, Massoud Dousti
2025 J jnl
Ensemble-Guided Distillation for Compact and Robust Acoustic Scene Classification on Edge Devices.
CoRR
Hossein Sharify, Behnam Raoufi, Mahdy Ramezani, Khosrow Hajsadeghi, Saeed Bagheri Shouraki
2024 J jnl
A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter.
J. Circuits Syst. Comput.
Abolfazl Roshanpanah, Pooya Torkzadeh, Khosrow Hajsadeghi, Massoud Dousti
2020 J jnl
Predicting scientific research trends based on link prediction in keyword networks.
J. Informetrics
Saman Behrouzi, Zahra Shafaeipour Sarmoor, Khosrow Hajsadeghi, Kaveh Kavousi
2019 J jnl
A 5.3-ps, 8-b Time to Digital Converter Using a New Gain-Reconfigurable Time Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Hasan Molaei, Khosrow Hajsadeghi
2018 J jnl
Design of low power comparator-reduced hybrid ADC.
Microelectron. J.
Hasan Molaei, Khosrow Hajsadeghi, Ata Khorami
2017 J jnl
A 1.6 ps 7 b time to digital converter in 0.18 µm CMOS technology.
Microelectron. J.
Hasan Molaei, Khosrow Hajsadeghi
2017 — conf
A low-power comparator-reduced flash ADC using dynamic comparators.
ICECS
Hasan Molaei, Khosrow Hajsadeghi
2017 — conf
Circuit design to improve security of telecommunication devices.
CCWC
Hengameh Bahrami, Khosrow Hajsadeghi
2016 — conf
A low power high resolution time to digital converter for ADPLL application.
MWSCAS
Hasan Molaei, Khosrow Hajsadeghi
2016 C conf
A wide dynamic range low power 2× time amplifier using current subtraction scheme.
ISCAS
Hasan Molaei, Ata Khorami, Khosrow Hajsadeghi
2015 — conf
A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application.
ICECS
Hasan Molaei, Ata Khorami, Mohammad S. Eslampanah Sendi, Khosrow Hajsadeghi
2014 — conf
12 bits, 40MS/s, low power pipelined SAR ADC.
MWSCAS
Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi
2014 J jnl
A Subthreshold Symmetric SRAM Cell With High Read Stability.
IEEE Trans. Circuits Syst. II Express Briefs
Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi
2014 J jnl
Fine logarithmic adaptive soft morphological algorithm for synthetic aperture radar image segmentation.
IET Image Process.
Mohaddeseh Koosha, Khosrow Hajsadeghi, Mohammad Koosha
2014 J jnl
Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell.
IEEE Trans. Circuits Syst. I Regul. Pap.
Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi
2013 — conf
A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM.
DTIS
Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi, Roghayeh Saeidi
2013 — conf
A novel low power 8T-cell sub-threshold SRAM with improved read-SNM.
DTIS
Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi, Roghayeh Saeidi
2012 — conf
New Operational Transconductance Amplifiers using current boosting.
MWSCAS
Mehdi Noormohammadi, Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi
2011 C conf
A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria.
ISCAS
Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi
2008 — conf
A clock boosting scheme for low voltage circuits.
ICECS
Amirehsan Behradfar, Saeed Zeinolabedinzadeh, Khosrow Hajsadeghi