Khawar Sarfraz

11 papers C 1Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
An Energy Efficient 4-bit SRAM Compute-in-Memory Macro With Tunable Reference Charge Injection SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ikramullah Shah, Huimin Zheng, Murad Abdullah, Khawar Sarfraz, Mansun Chan
2024 J jnl
An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Ikramullah Shah, Khawar Sarfraz, Mansun Chan
2021 — conf
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm.
ISSCC
Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan
2017 J jnl
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Khawar Sarfraz, Mansun Chan
2017 J jnl
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS.
IEEE J. Solid State Circuits
Khawar Sarfraz, Jin He, Mansun Chan
2016 J jnl
A compact low-power 4-port register file with grounded write bitlines and single-ended read operations.
Integr.
Khawar Sarfraz, Mansun Chan
2016 — conf
A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files.
MWSCAS
Khawar Sarfraz, Mansun Chan
2015 — conf
A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines.
ESSCIRC
Khawar Sarfraz, Mansun Chan
2015 — conf
Nanoscale register file circuit design - Challenges and opportunities.
ASICON
Khawar Sarfraz, Mansun Chan
2013 — conf
Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins.
ISVLSI
Khawar Sarfraz, Volkan Kursun
2011 C conf
A novel low-leakage 8T differential SRAM cell.
VLSI-SoC
Khawar Sarfraz