| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2015 | — | conf |
EMBC
|
| 2015 | J | jnl |
ACM Trans. Reconfigurable Technol. Syst.
|
| 2014 | J | jnl |
IEEE Micro
|
| 2013 | — | conf |
ReConFig
|
| 2013 | J | jnl |
SIGARCH Comput. Archit. News
|
| 2013 | J | jnl |
Digit. Signal Process.
|
| 2013 | — | conf |
Real-Time Image and Video Processing
|
| 2013 | J | jnl |
IEEE Trans. Computers
|
| 2013 | — | conf |
AHS
|
| 2013 | — | conf |
AHS
|
| 2013 | J | jnl |
IEEE Trans. Computers
|
| 2013 | C | conf |
ISCAS
|
| 2013 | — | conf |
EMBC
|
| 2013 | J | jnl |
Int. J. Reconfigurable Comput.
|
| 2012 | — | ed. |
AHS
|
| 2012 | — | conf |
ICB
|
| 2012 | — | conf |
ReConFig
|
| 2012 | — | conf |
AHS
|
| 2012 | B | conf |
FPL
|
| 2012 | — | conf |
AHS
|
| 2012 | B | conf |
FPL
|
| 2012 | B | conf |
FPL
|
| 2012 | J | jnl |
ACM Trans. Comput. Educ.
|
| 2012 | J | jnl |
SIGARCH Comput. Archit. News
|
| 2012 | J | jnl |
Int. J. Reconfigurable Comput.
|
| 2012 | J | jnl |
SIGARCH Comput. Archit. News
|
| 2012 | J | jnl |
Int. J. Reconfigurable Comput.
|
| 2012 | B | conf |
FPL
|
| 2012 | J | jnl |
J. Signal Process. Syst.
|
| 2012 | J | jnl |
Int. J. Reconfigurable Comput.
|
| 2012 | — | conf |
AHS
|
| 2012 | J | jnl |
J. Comput.
|
| 2012 | — | conf |
AHS
|
| 2011 | — | ed. |
AHS
|
| 2011 | — | conf |
ARC
|
| 2011 | — | conf |
AHS
|
| 2011 | — | conf |
AHS
|
| 2011 | — | conf |
AHS
|
| 2011 | J | jnl |
IEEE Embed. Syst. Lett.
|
| 2011 | — | conf |
AHS
|
| 2011 | — | conf |
ReConFig
|
| 2011 | — | conf |
AHS
|
| 2011 | — | conf |
AHS
|
| 2011 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2011 | — | conf |
High performance Intra-task parallelization of Multiple Sequence Alignments on CUDA-compatible GPUs.
AHS
|
| 2011 | — | conf |
ReConFig
|
| 2011 | B | conf |
FPL
|
| 2011 | — | conf |
ReConFig
|
| 2010 | — | ed. |
AHS
|
| 2010 | — | conf |
DASIP
|
| 2010 | — | conf |
FPT
|
| 2010 | — | conf |
AHS
|
| 2010 | Misc | conf |
ICCS
|
| 2010 | — | conf |
ERSA
|
| 2010 | — | conf |
ReConFig
|
| 2010 | J | jnl |
ACM Trans. Reconfigurable Technol. Syst.
|
| 2010 | — | conf |
ASAP
|
| 2010 | — | conf |
AHS
|
| 2010 | — | conf |
AHS
|
| 2009 | — | conf |
AHS
|
| 2009 | J | jnl |
A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment.
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2009 | A | conf |
FPGA
|
| 2009 | J | jnl |
Comput. Sci. Res. Dev.
|
| 2009 | — | conf |
SASP
|
| 2009 | — | conf |
AHS
|
| 2009 | — | conf |
AHS
|
| 2009 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2009 | — | conf |
AHS
|
| 2008 | — | conf |
AHS
|
| 2008 | J | jnl |
Eng. Lett.
|
| 2008 | — | conf |
FPT
|
| 2008 | J | jnl |
Eng. Lett.
|
| 2008 | J | jnl |
Eng. Lett.
|
| 2008 | C | conf |
BIBE
|
| 2008 | — | conf |
HPRCTA@SC
|
| 2008 | — | conf |
ERSA
|
| 2007 | Misc | conf |
FCCM
|
| 2007 | J | jnl |
J. Syst. Archit.
|
| 2007 | — | conf |
ICASSP (1)
|
| 2007 | — | conf |
ERSA
|
| 2006 | J | jnl |
Microprocess. Microsystems
|
| 2006 | J | jnl |
Signal Process.
|
| 2005 | A | conf |
FPGA
|
| 2005 | — | conf |
CAMP
|
| 2004 | — | conf |
ISVLSI
|
| 2004 | — | conf |
ISVLSI
|
| 2004 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2003 | Misc | conf |
FCCM
|
| 2003 | Misc | conf |
FCCM
|
| 2003 | A | conf |
FPGA
|
| 2003 | — | conf |
ICASSP (2)
|
| 2003 | A | conf |
FPGA
|
| 2003 | B | conf |
FPL
|
| 2003 | Misc | conf |
FCCM
|
| 2003 | B | conf |
FPL
|
| 2003 | A | conf |
FPGA
|
| 2003 | — | conf |
ISSPA (2)
|
| 2003 | J | jnl |
J. Electronic Imaging
|
| 2002 | B | conf |
FPL
|
| 2002 | — | conf |
FPT
|
| 2002 | — | conf |
DCV
|
| 2002 | — | conf |
ISCAS (4)
|
| 2002 | — | conf |
FPT
|
| 2002 | — | conf |
FPT
|
| 2002 | J | jnl |
Parallel Comput.
|
| 2001 | Misc | conf |
FCCM
|
| 2001 | Misc | conf |
FCCM
|
| 2000 | Misc | conf |
ICASSP
|
| 1999 | J | jnl |
J. Syst. Archit.
|