Khaled Benkrid

109 papers A 5B 8C 2Misc 8Journal 31Unranked 52

Year	Rank	Type	Title / Venue / Authors
2015	—	`conf`	Dynamic partial reconfiguration implementation of the SVM/KNN multi-classifier on FPGA for bioinformatics application. EMBC Hanaa M. Hussain, Khaled Benkrid, Huseyin Seker
2015	J	`jnl`	Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS). ACM Trans. Reconfigurable Technol. Syst. Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Raul Torrego, Tughrul Arslan
2014	J	`jnl`	R3TOS-Based Autonomous Fault-Tolerant Systems. IEEE Micro Xabier Iturbe, Ali Ebrahim, Khaled Benkrid, Chuan Hong, Tughrul Arslan, Jon Pérez, Didier Keymeulen, Marco D. Santambrogio
2013	—	`conf`	A platform for secure IP integration in Xilinx Virtex FPGAs. ReConFig Ali Ebrahim, Khaled Benkrid, Jalal Khalifat, Chuan Hong
2013	J	`jnl`	A run-time reconfigurable system for adaptive high performance efficient computing. SIGARCH Comput. Archit. News Chuan Hong, Khaled Benkrid, Mohd Nazrin Md. Isa, Xabier Iturbe
2013	J	`jnl`	A statistical framework to minimise and predict the range values of quantisation errors in fixed-point FIR filters architectures. Digit. Signal Process. Abdsamad Benkrid, Khaled Benkrid
2013	—	`conf`	Analysis and characterization of embedded vision systems for taxonomy formulation. Real-Time Image and Video Processing Muhammad Imran, Khaled Benkrid, Khursheed Khursheed, Naeem Ahmad, Mattias O'Nils, Najeem Lawal
2013	J	`jnl`	Guest Editors' introduction: Special section on adaptive hardware and systems. IEEE Trans. Computers Khaled Benkrid, Didier Keymeulen, Umeshkumar D. Patel, David Merodio Codinachs
2013	—	`conf`	Multiple-clone configuration of relocatable partial bitstreams in Xilinx Virtex FPGAs. AHS Ali Ebrahim, Khaled Benkrid, Xabier Iturbe, Chuan Hong
2013	—	`conf`	Preface. AHS Khaled Benkrid, Didier Keymeulen, David Merodio, Michael Newell, Rainer Wansch, Umeshkumar D. Patel, Ahmet T. Erdogan, Niels Hadaschik, Luca Sterpone, Jelle Poupaert, Massimo Violante
2013	J	`jnl`	R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs. IEEE Trans. Computers Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Raul Torrego, Imanol Martinez, Tughrul Arslan, Jon Pérez
2013	C	`conf`	Reconfigurable feeding network for GSM/GPS/3G/WiFi and global LTE applications. ISCAS Wei Zhou, Tughrul Arslan, Khaled Benkrid, Ahmed O. El-Rayis, Nakul Haridas
2013	—	`conf`	Reconfiguration-based implementation of SVM classifier on FPGA for Classifying Microarray data. EMBC Hanaa M. Hussain, Khaled Benkrid, Huseyin Seker
2013	J	`jnl`	Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence. Int. J. Reconfigurable Comput. Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Tughrul Arslan, Imanol Martinez
2012	—	`ed.`	2012 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2012, Erlangen, Germany, June 25-28, 2012 AHS Umeshkumar D. Patel, Khaled Benkrid, David Merodio
2012	—	`conf`	A generic computer platform for efficient iris recognition. ICB Chris Ponder, Khaled Benkrid, Abdsamad Benkrid
2012	—	`conf`	A novel efficient FPGA architecture for HMMER acceleration. ReConFig Mohd Nazrin Md. Isa, Khaled Benkrid, Thomas Clayton
2012	—	`conf`	A novel high-performance fault-tolerant ICAP controller. AHS Ali Ebrahim, Khaled Benkrid, Xabier Iturbe, Chuan Hong
2012	B	`conf`	An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfiguration. FPL Hanaa M. Hussain, Khaled Benkrid, Chuan Hong, Huseyin Seker
2012	—	`conf`	An adaptive implementation of a dynamically reconfigurable K-nearest neighbour classifier on FPGA. AHS Hanaa M. Hussain, Khaled Benkrid, Huseyin Seker
2012	B	`conf`	Data coding functions for Software Defined Radios implemented on R3TOS. FPL Raul Torrego, Inaki Val, Eñaut Muxika, Xabier Iturbe, Khaled Benkrid
2012	B	`conf`	Design and implementation of fault-tolerant soft processors on FPGAs. FPL Chuan Hong, Khaled Benkrid, Xabier Iturbe, Ali Ebrahim
2012	J	`jnl`	Digital Hardware Design Teaching: An Alternative Approach. ACM Trans. Comput. Educ. Khaled Benkrid, Thomas Clayton
2012	J	`jnl`	Efficient architecture and scheduling technique for pairwise sequence alignment. SIGARCH Comput. Archit. News Mohd Nazrin Md. Isa, Khaled Benkrid, Thomas Clayton
2012	J	`jnl`	High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP. Int. J. Reconfigurable Comput. Khaled Benkrid, Ali Akoglu, Cheng Ling, Yang Song, Ying Liu, Xiang Tian
2012	J	`jnl`	High performance phylogenetic analysis on CUDA-compatible GPUs. SIGARCH Comput. Archit. News Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
2012	J	`jnl`	High-Performance Reconfigurable Computing. Int. J. Reconfigurable Comput. Khaled Benkrid, Esam El-Araby, Miaoqing Huang, Kentaro Sano, Thomas Steinke
2012	B	`conf`	IP-XACT extensions for IP interoperability guarantees and software model generation. FPL Thomas P. Perry, Richard L. Walke, Rob Payne, Stefan Petko, Khaled Benkrid
2012	J	`jnl`	Implementation of the Longstaff and Schwartz American Option Pricing Model on FPGA. J. Signal Process. Syst. Xiang Tian, Khaled Benkrid
2012	J	`jnl`	Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs. Int. J. Reconfigurable Comput. Hanaa M. Hussain, Khaled Benkrid, Ali Ebrahim, Ahmet T. Erdogan, Huseyin Seker
2012	—	`conf`	Online clock routing in Xilinx FPGAs for high-performance and reliability. AHS Xabier Iturbe, Khaled Benkrid, Raul Torrego, Ali Ebrahim, Tughrul Arslan
2012	J	`jnl`	Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA-Based Supercomputer. J. Comput. Server Kasap, Khaled Benkrid
2012	—	`conf`	Real-time CCSDS lossless adaptive hyperspectral image compression on parallel GPGPU & multicore processor systems. AHS Ben Hopson, Khaled Benkrid, Didier Keymeulen, Nazeeh Aranki
2011	—	`ed.`	2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011, San Diego, California, USA, June 6-9, 2011 AHS David Merodio, Tughrul Arslan, Umeshkumar D. Patel, Didier Keymeulen, Khaled Benkrid, Ahmet T. Erdogan, Michael Newell, Luca Fossati, Duane Armstrong
2011	—	`conf`	A (Fault-Tolerant) ARC Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Mikel Azkarate-askasua, Imanol Martinez
2011	—	`conf`	A high performance implementation for Molecular Dynamics simulations on a FPGA supercomputer. AHS Server Kasap, Khaled Benkrid
2011	—	`conf`	An FPGA task allocator with preliminary First-Fit 2D packing algorithms. AHS Chuan Hong, Khaled Benkrid, Xabier Iturbe, Ahmet T. Erdogan, Tughrul Arslan
2011	—	`conf`	An FPGA-based parameterised and scalable optimal solutions for pairwise biological sequence analysis. AHS Mohd Nazrin Md. Isa, Khaled Benkrid, Thomas Clayton, Cheng Ling, Ahmet T. Erdogan
2011	J	`jnl`	Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems. IEEE Embed. Syst. Lett. Chuan Hong, Khaled Benkrid, Xabier Iturbe, Ali Ebrahim, Tughrul Arslan
2011	—	`conf`	Embedded high-speed Model Predictive Controller on a FPGA. AHS Koldo Basterretxea, Khaled Benkrid
2011	—	`conf`	Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence. ReConFig Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Chuan Hong, Imanol Martinez
2011	—	`conf`	Enabling FPGAs for future deep space exploration missions: Improving fault-tolerance and computation density with R3TOS. AHS Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Chuan Hong, Ahmet T. Erdogan, Imanol Martinez
2011	—	`conf`	FPGA implementation of K-means algorithm for bioinformatics application: An accelerated approach to clustering Microarray data. AHS Hanaa M. Hussain, Khaled Benkrid, Huseyin Seker, Ahmet T. Erdogan
2011	J	`jnl`	High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable Hardware. IEEE Trans. Very Large Scale Integr. Syst. Server Kasap, Khaled Benkrid
2011	—	`conf`	High performance Intra-task parallelization of Multiple Sequence Alignments on CUDA-compatible GPUs. AHS Cheng Ling, Khaled Benkrid, Ahmet T. Erdogan
2011	—	`conf`	Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs. ReConFig Hanaa M. Hussain, Khaled Benkrid, Ahmet T. Erdogan, Huseyin Seker
2011	B	`conf`	Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs. FPL Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Raul Torrego, Imanol Martinez
2011	—	`conf`	Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable Computing. ReConFig Xabier Iturbe, Khaled Benkrid, Ali Ebrahim, Chuan Hong, Tughrul Arslan, Imanol Martinez
2010	—	`ed.`	2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010, Anaheim, California, USA, June 15-18, 2010 AHS Tughrul Arslan, Didier Keymeulen, David Merodio, Khaled Benkrid, Ahmet T. Erdogan, Umeshkumar D. Patel
2010	—	`conf`	A Roadmap for Autonomous Fault-Tolerant Systems. DASIP Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua, Marco D. Santambrogio
2010	—	`conf`	ATB: Area-Time response Balancing algorithm for scheduling real-time hardware tasks. FPT Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua
2010	—	`conf`	Adaptive and evolvable hardware security architectures. AHS Wael Adi, Khaled Benkrid
2010	Misc	`conf`	Design and implementation of a CUDA-compatible GPU-based core for gapped BLAST algorithm. ICCS Cheng Ling, Khaled Benkrid
2010	—	`conf`	Evolutionary Dynamic Allocation of Relocatable Modules onto Partially Damaged Xilinx FPGAs. ERSA Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua, Alicia Morales-Reyes
2010	—	`conf`	Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations. ReConFig Xiang Tian, Khaled Benkrid
2010	J	`jnl`	High-Performance Quasi-Monte Carlo Financial Simulation: FPGA vs. GPP vs. GPU. ACM Trans. Reconfigurable Technol. Syst. Xiang Tian, Khaled Benkrid
2010	—	`conf`	Highly efficient mapping of the Smith-Waterman algorithm on CUDA-compatible GPUs. ASAP Keisuke Dohi, Khaled Benkrid, Cheng Ling, Tsuyoshi Hamada, Yuichiro Shibata
2010	—	`conf`	R3TOS: A reliable reconfigurable real-time operating system. AHS Xabier Iturbe, Khaled Benkrid, Ahmet T. Erdogan, Tughrul Arslan, Mikel Azkarate-askasua, Imanol Martinez, Antonio Perez
2010	—	`conf`	Ultimate design security in self-reconfiguring non-volatile environments. AHS Wael Adi, Khaled Benkrid
2009	—	`conf`	A Comparative Study on ASIC, FPGAs, GPUs and General Purpose Processors in the O(N^2) Gravitational N-body Simulation. AHS Tsuyoshi Hamada, Khaled Benkrid, Keigo Nitadori, Makoto Taiji
2009	J	`jnl`	A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment. IEEE Trans. Very Large Scale Integr. Syst. Khaled Benkrid, Ying Liu, Abdsamad Benkrid
2009	A	`conf`	A high performance fpga-based implementation of position specific iterated blast. FPGA Server Kasap, Khaled Benkrid, Ying Liu
2009	J	`jnl`	A novel multiple-walk parallel algorithm for the Barnes-Hut treecode on GPUs - towards cost effective, high performance N-body simulation. Comput. Sci. Res. Dev. Tsuyoshi Hamada, Keigo Nitadori, Khaled Benkrid, Yousuke Ohno, Gentaro Morimoto, Tomonari Masada, Yuichiro Shibata, Kiyoshi Oguri, Makoto Taiji
2009	—	`conf`	A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs. SASP Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
2009	—	`conf`	An FPGA-Based Web Server for High Performance Biological Sequence Alignment. AHS Ying Liu, Khaled Benkrid, Abdsamad Benkrid, Server Kasap
2009	—	`conf`	Mersenne Twister Random Number Generation on FPGA, CPU and GPU. AHS Xiang Tian, Khaled Benkrid
2009	J	`jnl`	Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension. IEEE Trans. Very Large Scale Integr. Syst. Abdsamad Benkrid, Khaled Benkrid
2009	—	`conf`	Rapid Prototyping of an Improved Cholesky Decomposition Based MIMO Detector on FPGAs. AHS Xuezheng Chu, Khaled Benkrid, John Thompson
2008	—	`conf`	A High Performance Reconfigurable Core for Motif Searching Using Profile HMM. AHS Khaled Benkrid, Panagiotis Velentzas, Server Kasap
2008	J	`jnl`	Design and Implementation of an FPGA-based Core for Gapped BLAST Sequence Alignment with the Two-Hit Method. Eng. Lett. Server Kasap, Khaled Benkrid, Ying Liu
2008	—	`conf`	Design and implementation of a high performance financial Monte-Carlo simulation engine on an FPGA supercomputer. FPT Xiang Tian, Khaled Benkrid
2008	J	`jnl`	HIDE+: A Logic Based Hardware Development Environment. Eng. Lett. Abdsamad Benkrid, Khaled Benkrid
2008	J	`jnl`	High Performance Monte-Carlo Based Option Pricing on FPGAs. Eng. Lett. Xiang Tian, Khaled Benkrid, Xiaochen Gu
2008	C	`conf`	High performance FPGA-based core for BLAST sequence alignment with the two-hit method. BIBE Server Kasap, Khaled Benkrid, Ying Liu
2008	—	`conf`	Massively Parallelized Quasi-Monte Carlo financial Simulation on a FPGA Supercomputer. HPRCTA@SC Xiang Tian, Khaled Benkrid
2008	—	`conf`	Multi-Criteria Optimization and Performance Measurement of Domain-Specific Reconfigurable Architectures Targeting Image and Video Processing Applications. ERSA Arjun K. Pai, Khaled Benkrid
2007	Misc	`conf`	Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment. FCCM Khaled Benkrid, Ying Liu, Abdsamad Benkrid
2007	J	`jnl`	Efficient FPGA hardware development: A multi-language approach. J. Syst. Archit. Khaled Benkrid, Abdsamad Benkrid, Samir Belkacemi
2007	—	`conf`	High Performance Biosequence Database Scanning using FPGAs. ICASSP (1) Khaled Benkrid, Ying Liu, Abdsamad Benkrid
2007	—	`conf`	Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications. ERSA Arjun K. Pai, Khaled Benkrid
2006	J	`jnl`	HIDE: A hardware intelligent description environment. Microprocess. Microsystems Khaled Benkrid, Samir Belkacemi, Abdsamad Benkrid
2006	J	`jnl`	Handling finite length signals borders in two-channel multirate filter banks for perfect reconstruction. Signal Process. Abdsamad Benkrid, Khaled Benkrid
2005	A	`conf`	An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only). FPGA Khaled Benkrid, Samir Belkacemi
2005	—	`conf`	Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic. CAMP Arjun K. Pai, Khaled Benkrid, Danny Crookes
2004	—	`conf`	A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs. ISVLSI S. Sukhsawas, Khaled Benkrid
2004	—	`conf`	Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. ISVLSI Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
2004	J	`jnl`	From application descriptions to hardware in seconds: a logic-based approach to bridging the gap. IEEE Trans. Very Large Scale Integr. Syst. Khaled Benkrid, Danny Crookes
2003	Misc	`conf`	A Logic Based Hardware Development Environment. FCCM Samir Belkacemi, Khaled Benkrid, Danny Crookes
2003	Misc	`conf`	A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. FCCM Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
2003	A	`conf`	A logic based approach to hardware abstraction. FPGA Khaled Benkrid, Samir Belkacemi, Danny Crookes
2003	—	`conf`	A novel approach for diminishing and predicting the error dynamic range in finite wordlength FIR based architectures. ICASSP (2) Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
2003	A	`conf`	A single-FPGA implementation of image connected component labelling. FPGA Khaled Benkrid, S. Sukhsawas, Danny Crookes, Samir Belkacemi
2003	B	`conf`	An FPGA-Based Image Connected Component Labeller. FPL Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid
2003	Misc	`conf`	Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA. FCCM Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
2003	B	`conf`	Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. FPL Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
2003	A	`conf`	Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA. FPGA Abdsamad Benkrid, Danny Crookes, Khaled Benkrid
2003	—	`conf`	Minimisation and prediction of the error dynamic range in finite wordlength FIR based architectures: application to the 2-D orthogonal DWT. ISSPA (2) Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
2003	J	`jnl`	New bit-level algorithm for general purpose median filtering. J. Electronic Imaging Khaled Benkrid, Danny Crookes
2002	B	`conf`	A Prolog-Based Hardware Development Environment. FPL Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, Samir Belkacemi
2002	—	`conf`	A multiplier-less FPGA core for image algebra neighbourhood operations. FPT Khaled Benkrid
2002	—	`conf`	Design and implementation of a 2D convolution core for video applications on FPGAs. DCV Khaled Benkrid, Samir Belkacemi
2002	—	`conf`	Design and implementation of a novel algorithm for general purpose median filtering on FPGAs. ISCAS (4) Khaled Benkrid, Danny Crookes, Abdsamad Benkrid
2002	—	`conf`	Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs. FPT Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
2002	—	`conf`	HIDE: a logic based hardware intelligent description environment. FPT Samir Belkacemi, Khaled Benkrid, Danny Crookes
2002	J	`jnl`	Towards a general framework for FPGA based image processing using hardware skeletons. Parallel Comput. Khaled Benkrid, Danny Crookes, Abdsamad Benkrid
2001	Misc	`conf`	Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA. FCCM Abdsamad Benkrid, Danny Crookes, Khaled Benkrid
2001	Misc	`conf`	High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons. FCCM Khaled Benkrid, Danny Crookes, J. Smith, Abdsamad Benkrid
2000	Misc	`conf`	High level programming for real time FPGA based video processing. ICASSP Khaled Benkrid, Danny Crookes, J. Smith, Abdsamad Benkrid
1999	J	`jnl`	A high level FPGA-based abstract machine for image processing. J. Syst. Archit. Ahmed Bouridane, Danny Crookes, Paul Donachy, Khalid Alotaibi, Khaled Benkrid