Kewal K. Saluja

252 papers A* 6A 25B 12C 10Misc 49Journal 88Unranked 62
YearRankTypeTitle / Venue / Authors
2021 J jnl
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method.
J. Electron. Test.
Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
2020 Misc conf
Fault Tolerance through Invariant Checking for the Lanczos Eigensolver.
VLSID
Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
2018 — conf
Fault Tolerant Cholesky Factorization on GPUs.
FTXS@SC
Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
2017 J jnl
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line.
IEICE Trans. Inf. Syst.
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2017 J jnl
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging.
J. Electron. Test.
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
2017 A conf
Exploiting path delay test generation to develop better TDF tests for small delay defects.
ITC
Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja
2017 — conf
Identifying high variability speed-limiting paths under aging.
LATS
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
2016 — conf
Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations.
ATS
Parameswaran Ramanathan, Kewal K. Saluja
2016 J jnl
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays.
IPSJ Trans. Syst. LSI Des. Methodol.
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2016 Misc conf
Digital Testing - Basics to Advanced Research Issues.
VLSID
Kewal K. Saluja
2016 Misc conf
Fault Tolerance through Invariant Checking for Iterative Solvers.
VLSID
Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan
2016 J jnl
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model.
ACM Trans. Embed. Comput. Syst.
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
2015 — conf
A Methodology for Identifying High Timing Variability Paths in Complex Designs.
ATS
Virendra Singh, Adit D. Singh, Kewal K. Saluja
2015 — conf
Diagnosis of Delay Faults Considering Hazards.
ISVLSI
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2015 Misc conf
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints.
VLSID
Spencer K. Millican, Kewal K. Saluja
2015 — conf
Privacy Assurance in Data-Aggregation for Multiple MAX Transactions.
COMPSAC Workshops
Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja
2015 Misc conf
Thermal Extension of the Total Bandwidth Server.
VLSID
Rehan Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, Parameswaran Ramanathan, Kewal K. Saluja
2015 — conf
Transient Fault Resilient QR Factorization on GPUs.
FTXS@HPDC
Felix Loh, Parameswaran Ramanathan, Kewal K. Saluja
2014 Misc conf
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits.
VLSID
Spencer K. Millican, Kewal K. Saluja
2014 Misc conf
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities.
VLSID
Spencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja
2014 — conf
Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults.
ISVLSI
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2014 B conf
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks.
ECRTS
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
2014 J jnl
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling.
J. Electron. Test.
Spencer K. Millican, Kewal K. Saluja
2014 Misc conf
Temperature Minimization Using Power Redistribution in Embedded Systems.
VLSID
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
2013 — conf
DRMA: dynamically reconfigurable MPSoC architecture.
ACM Great Lakes Symposium on VLSI
Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja
2013 — conf
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation.
Asian Test Symposium
Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja
2013 — conf
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling.
Asian Test Symposium
Spencer K. Millican, Kewal K. Saluja
2013 B conf
On thermal utilization of periodic task sets in uni-processor systems.
RTCSA
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja
2013 Misc conf
Privacy Assurances in Multiple Data-Aggregation Transactions.
ICISC
Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja
2013 Misc conf
Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems.
VLSI Design
Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao
2013 J jnl
Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment.
IEICE Trans. Inf. Syst.
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2012 C conf
Diagnosis for Bridging Faults on Clock Lines.
PRDC
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2012 Misc conf
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate.
VLSI Design
Warin Sootkaneung, Kewal K. Saluja
2012 — conf
Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits.
Asian Test Symposium
Spencer K. Millican, Kewal K. Saluja
2011 — conf
A low cost approach to calibrate on-chip thermal sensors.
ISQED
Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja
2011 J jnl
Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors.
Ad Hoc Networks
Yen-Ting Lin, Kewal K. Saluja, Seapahn Megerian
2011 C conf
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors.
ICCD
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2011 J jnl
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach.
J. Electron. Test.
Chunhua Yao, Kewal K. Saluja, Parmesh Ramanathan
2011 B conf
Enhancement of Clock Delay Faults Testing.
ETS
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2011 — conf
Fault simulation and test generation for clock delay faults.
ASP-DAC
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2011 C conf
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations.
DDECS
Tsuyoshi Iwagaki, Kewal K. Saluja
2011 — conf
On Detecting Transition Faults in the Presence of Clock Delay Faults.
Asian Test Symposium
Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
2011 J jnl
Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
2011 J jnl
Routing TCP Flows in Underwater Mesh Networks.
IEEE J. Sel. Areas Commun.
Chin-Ya Huang, Parameswaran Ramanathan, Kewal K. Saluja
2011 — conf
SEU tolerant SRAM cell.
ISQED
Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
2011 — conf
Soft error reduction through gate input dependent weighted sizing in combinational circuits.
ISQED
Warin Sootkaneung, Kewal K. Saluja
2011 — conf
Temperature Dependent Test Scheduling for Multi-core System-on-Chip.
Asian Test Symposium
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
2011 Misc conf
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors.
VLSI Design
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
2010 J jnl
A Study of Capture-Safe Test Generation Flow for At-Speed Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2010 — conf
Collaborative patrolling for target detection using mobile sensor networks.
WCSP
Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
2010 B conf
Connected Barrier Coverage on a Narrow Band: Analysis and Deployment.
SECON
Yen-Ting Lin, Kewal K. Saluja, Parameswaran Ramanathan
2010 — conf
Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST.
Asian Test Symposium
Hiroshi Yokoyama, Hideo Tamamoto, Kewal K. Saluja
2010 C conf
Detection of inter-port bridging faults in dual-port memories.
ISCAS
Ho-Yong Choi, Kewal K. Saluja
2010 A conf
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding.
DSN
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010 — conf
Energy-efficient redundant execution for chip multiprocessors.
ACM Great Lakes Symposium on VLSI
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010 — conf
Gate input reconfiguration for combating soft errors in combinational circuits.
DSN Workshops
Warin Sootkaneung, Kewal K. Saluja
2010 J jnl
Modeling latency - lifetime trade-off for target detection in mobile sensor networks.
ACM Trans. Sens. Networks
Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja
2010 B conf
Modified T-Flip-Flop based scan cell for RAS.
ETS
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh
2010 A conf
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors.
DATE
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
2010 Misc conf
On Minimization of Test Application Time for RAS.
VLSI Design
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh
2010 A conf
On techniques for handling soft errors in digital circuits.
ITC
Warin Sootkaneung, Kewal K. Saluja
2010 A* conf
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations.
DAC
Lin Xie, Azadeh Davoodi, Kewal K. Saluja
2010 — conf
SEU tolerant SRAM for FPGA applications.
FPT
Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita
2010 C conf
Test application time minimization for RAS using basis optimization of column decoder.
ISCAS
A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh
2009 J jnl
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2009 J jnl
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.
Inf. Media Technol.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu
2009 J jnl
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.
IPSJ Trans. Syst. LSI Des. Methodol.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2009 B conf
Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions.
SECON
Chao Wang, Parmesh Ramanathan, Kewal K. Saluja
2009 — conf
DX-compactor: distributed X-compaction for SoCs.
ACM Great Lakes Symposium on VLSI
Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja
2009 Misc conf
False Path Aware Timing Yield Estimation under Variability.
VTS
Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar
2009 J jnl
Low-Area Wrapper Cell Design for Hierarchical SoC Testing.
J. Electron. Test.
Kyuchull Kim, Kewal K. Saluja
2009 J jnl
Modeling Detection Latency with Collaborative Mobile Sensing Architecture.
IEEE Trans. Computers
Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
2009 — conf
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies.
Asian Test Symposium
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
2009 A conf
Power and thermal constrained test scheduling.
ITC
Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
2009 Misc conf
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.
VLSI Design
Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar
2008 B conf
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.
ETS
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2008 A conf
An accurate flip-flop selection technique for reducing logic SER.
DSN
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
2008 J jnl
Analysis and test procedures for NOR flash memory defects.
Microelectron. Reliab.
Mohammad Gh. Mohammad, Kewal K. Saluja
2008 B conf
Calibrating Nonlinear Mobile Sensors.
SECON
Chao Wang, Parmesh Ramanathan, Kewal K. Saluja
2008 J jnl
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools.
IEICE Trans. Inf. Syst.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008 A* conf
Implementing high availability memory with a duplication cache.
MICRO
Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan
2008 — conf
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults.
ATS
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008 J jnl
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.
J. Electron. Test.
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2008 J jnl
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2008 — conf
Moments Based Blind Calibration in Mobile Sensor Networks.
ICC
Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja
2008 Misc conf
NBTI Degradation: A Problem or a Scare?
VLSI Design
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang
2008 Misc conf
Testing Flash Memories for Tunnel Oxide Defects.
VLSI Design
Mohammad Gh. Mohammad, Kewal K. Saluja
2007 J jnl
A Novel ATPG Method for Capture Power Reduction during Scan Testing.
IEICE Trans. Inf. Syst.
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2007 J jnl
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.
IEICE Trans. Inf. Syst.
Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara
2007 — conf
Combating NBTI Degradation via Gate Sizing.
ISQED
Xiangning Yang, Kewal K. Saluja
2007 A* conf
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.
DAC
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
2007 J jnl
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
IEEE Trans. Very Large Scale Integr. Syst.
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
2007 Misc conf
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.
VLSI Design
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu
2007 Misc conf
On NBTI Degradation Process in Digital Logic Circuits.
VLSI Design
Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja
2007 — conf
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator.
ATS
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2007 Misc conf
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.
VLSI Design
Kim T. Le, Dong Hyun Baik, Kewal K. Saluja
2006 Misc conf
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
VTS
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
2006 J jnl
A New Method for Low-Capture-Power Test Generation for Scan Testing.
IEICE Trans. Inf. Syst.
Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2006 J jnl
A Per-Test Fault Diagnosis Method Based on the
IEICE Trans. Inf. Syst.
Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita
2006 — conf
Analytic modeling of detection latency in mobile sensor networks.
IPSN
Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
2006 — conf
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.
ASP-DAC
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
2006 — conf
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
ATS
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
2006 — conf
Diagnosis of Transistor Shorts in Logic Test Environment.
ATS
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu
2006 J jnl
Energy Estimation of the Memory Subsystem in Multiprocessor Systems.
J. Low Power Electron.
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
2006 J jnl
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.
IEICE Trans. Inf. Syst.
Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
2006 C conf
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
ICCD
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
2006 J jnl
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2006 B conf
Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles.
GLOBECOM
Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja
2006 Misc conf
Test Cost Reduction Using Partitioned Grid Random Access Scan.
VLSI Design
Dong Hyun Baik, Kewal K. Saluja
2006 J jnl
Vulnerability of Surveillance Networks to Faults.
Int. J. Distributed Sens. Networks
Tai-Lin Chin, Thomas Clouqueur, Parameswaran Ramanathan, Kewal K. Saluja
2005 — conf
A Class of Linear Space Compactors for Enhanced Diagnostic.
Asian Test Symposium
Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja
2005 J jnl
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
2005 J jnl
Combinational automatic test pattern generation for acyclic sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
2005 J jnl
Delay Fault Testing of Processor Cores in Functional Mode.
IEICE Trans. Inf. Syst.
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005 A conf
Design and analysis of multiple weight linear compactors of responses containing unknown values.
ITC
Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara
2005 J jnl
Efficient Test Set Modification for Capture Power Reduction.
J. Low Power Electron.
Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
2005 B conf
Exposure for collaborative detection using mobile sensor networks.
MASS
Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja, Kuang-Ching Wang
2005 Misc conf
False Path and Clock Scheduling Based Yield-Aware Gate Sizing.
VLSI Design
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2005 J jnl
Fault Diagnosis of Physical Defects Using Unknown Behavior Model.
J. Comput. Sci. Technol.
Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
2005 — conf
Instruction-based delay fault self-testing of pipelined processor cores.
ISCAS (6)
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005 A conf
Low-capture-power test generation for scan-based at-speed testing.
ITC
Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005 J jnl
On Design for I
IEICE Trans. Inf. Syst.
Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
2005 Misc conf
On Low-Capture-Power Test Generation for Scan Testing.
VTS
Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005 J jnl
Optimizing program disturb fault tests using defect-based testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohammad Gh. Mohammad, Kewal K. Saluja
2005 A conf
Progressive random access scan: a simultaneous solution to test power, test data volume and test time.
ITC
Dong Hyun Baik, Kewal K. Saluja
2005 Misc conf
SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits.
VLSI Design
Marong Phadoongsidhi, Kewal K. Saluja
2005 — conf
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.
Asian Test Symposium
Dong Hyun Baik, Kewal K. Saluja
2005 B conf
Testing Superscalar Processors in Functional Mode.
FPL
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005 J jnl
Yield-Driven, False-Path-Aware Clock Skew Scheduling.
IEEE Des. Test Comput.
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2004 A conf
A yield improvement methodology using pre- and post-silicon statistical clock scheduling.
ICCAD
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2004 B conf
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.
ETS
Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy
2004 J jnl
Fault Tolerance in Collaborative Sensor Networks for Target Detection.
IEEE Trans. Computers
Thomas Clouqueur, Kewal K. Saluja, Parameswaran Ramanathan
2004 Misc conf
Instruction-Based Delay Fault Self-Testing of Processor Cores.
VLSI Design
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2004 A conf
On per-test fault diagnosis using the X-fault model.
ICCAD
Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2004 Misc conf
Random Access Scan: A solution to test power, test data volume and test time.
VLSI Design
Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
2004 Misc conf
Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults.
VLSI Design
Marong Phadoongsidhi, Kewal K. Saluja
2004 A conf
Testing Micropipelined Asynchronous Circuits.
ITC
Matthew L. King, Kewal K. Saluja
2004 C conf
Testing of Hard Faults in Simultaneous Multithreaded Processors.
IOLTS
Eric F. Weglarz, Kewal K. Saluja, T. M. Mak
2003 Misc conf
Electrical Model For Program Disturb Faults in Non-Volatile Memories.
VLSI Design
Mohammad Gh. Mohammad, Kewal K. Saluja
2003 C conf
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits.
ICCD
Marong Phadoongsidhi, Kewal K. Saluja
2003 Misc conf
Exclusive Test and its Applications to Fault Diagnosis.
VLSI Design
Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja
2003 — conf
Fault Diagnosis for Physical Defects of Unknown Behaviors.
Asian Test Symposium
Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
2003 — conf
Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits.
Asian Test Symposium
Kewal K. Saluja
2003 J jnl
Sensor Deployment Strategy for Detection of Targets Traversing a Region.
Mob. Networks Appl.
Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja
2003 — conf
Software-Based Delay Fault Testing of Processor Cores.
Asian Test Symposium
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2003 — conf
Stress Test for Disturb Faults in Non-Volatile Memories.
Asian Test Symposium
Mohammad Gh. Mohammad, Kewal K. Saluja
2002 — conf
A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits.
Asian Test Symposium
Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja
2002 C conf
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.
PRDC
Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
2002 — conf
Estimation of Maximum Power-Up Current.
ASP-DAC/VLSI Design
Fei Li, Lei He, Kewal K. Saluja
2002 — conf
Minimizing Energy Consumption for High-Performance Processing.
ASP-DAC/VLSI Design
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
2002 — conf
Multiple Faults: Modeling, Simulation and Test.
ASP-DAC/VLSI Design
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
2002 J jnl
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu
2002 — conf
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.
Asian Test Symposium
Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
2002 — conf
Sensor deployment strategy for target detection.
WSNA
Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja
2001 Misc conf
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.
VLSI Design
Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
2001 A conf
Combinational test generation for various classes of acyclic sequential circuits.
ITC
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
2001 Misc conf
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows.
VLSI Design
Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi
2001 J jnl
Fault Models and Test Procedures for Flash Memory Disturbances.
J. Electron. Test.
Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap
2001 Misc conf
Flash Memory Disturbances: Modeling and Test.
VTS
Mohammad Gh. Mohammad, Kewal K. Saluja
2001 A conf
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits.
ITC
Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
2001 — conf
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits.
Asian Test Symposium
Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu
2001 Misc conf
Testable Sequential Circuit Design: A Partition and Resynthesis Approach.
VTS
Richard M. Chou, Kewal K. Saluja
2000 J jnl
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.
J. Electron. Test.
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000 Misc conf
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.
VLSI Design
Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara
2000 A conf
Fault Tolerance through Re-Execution in Multiscalar Architecture.
DSN
Faisal Rashid, Kewal K. Saluja, Parameswaran Ramanathan
2000 — conf
Fault models and test generation for IDDQ testing: embedded tutorial.
ASP-DAC
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
2000 J jnl
Static test compaction for IDDQ testing of bridging faults in sequential circuits.
Syst. Comput. Jpn.
Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
2000 Misc conf
Testing Flash Memories.
VLSI Design
Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap
1999 — conf
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability.
Great Lakes Symposium on VLSI
Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
1999 Misc conf
Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.
VLSI Design
Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
1999 — conf
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.
Asian Test Symposium
Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
1998 J jnl
A Heuristic Measure to Maximize Detected Faults per Test.
J. Electron. Test.
Kim T. Le, Kewal K. Saluja
1998 J jnl
A Novel Approach to Random Pattern Testing of Sequential Circuits.
IEEE Trans. Computers
Lama Nachman, Kewal K. Saluja, Shambhu J. Upadhyaya, Robert Reuse
1998 — conf
Design for Diagnosability of CMOS Circuits.
Asian Test Symposium
Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita
1998 — conf
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.
Asian Test Symposium
Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita
1998 Misc conf
On Test Pattern Compaction Using Random Pattern Fault Simulation.
VLSI Design
Seiji Kajihara, Kewal K. Saluja
1998 J jnl
Sequential test generators: past, present and future.
Integr.
Yong Chang Kim, Kewal K. Saluja
1997 J jnl
Guest Editorial.
J. Electron. Test.
Kwang-Ting Cheng, Kewal K. Saluja, Hans-Joachim Wunderlich
1997 J jnl
Scheduling tests for VLSI systems under power constraints.
IEEE Trans. Very Large Scale Integr. Syst.
Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
1997 Misc conf
Sequential Circuit Testing: From DFT to SFT.
VLSI Design
Richard M. Chou, Kewal K. Saluja
1996 A conf
A new method towards achieving global optimality in technology mapping.
ICCAD
Xiaoqing Wen, Kewal K. Saluja
1996 J jnl
HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits.
VLSI Design
Kyuchull Kim, Kewal K. Saluja
1996 J jnl
Incorporating performance and testability constraints during binding in high-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
1996 Misc conf
Methods for Dynamic Test Vector compaction in Sequential Test Generation.
VLSI Design
Timothy John Lambert, Kewal K. Saluja
1996 — conf
Random Pattern Testing for Sequential Circuits Revisited.
FTCS
Lama Nachman, Kewal K. Saluja, Shambhu J. Upadhyaya, Robert Reuse
1996 J jnl
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Manoj Franklin, Kewal K. Saluja
1995 Misc conf
An optimized testable architecture for finite state machines.
VTS
Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja
1995 Misc conf
Fast computation of MISR signatures.
VLSI Design
Manoj Franklin, Kewal K. Saluja, Kyuchull Kim
1995 — conf
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan.
FTCS
Ning Jiang, Richard M. Chou, Kewal K. Saluja
1995 — conf
Test application time reduction for scan based sequential circuits.
Great Lakes Symposium on VLSI
Hao Zheng, Kewal K. Saluja, Rajiv Jain
1995 J jnl
Test application time reduction for sequential circuits with scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Soo Young Lee, Kewal K. Saluja
1994 Misc conf
An Algorithm to Test Reconfigured RAMs.
VLSI Design
Manoj Franklin, Kewal K. Saluja
1994 — conf
Behavioral Synthesis of Testable Designs.
FTCS
Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
1994 J jnl
Hypergraph Coloring and Reconfigured RAM Testing.
IEEE Trans. Computers
Manoj Franklin, Kewal K. Saluja
1994 J jnl
Incorporating testability considerations in high-level synthesis.
J. Electron. Test.
Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
1994 J jnl
On-chip testing of random access memories.
J. Electron. Test.
Kewal K. Saluja
1994 Misc conf
Power Constraint Scheduling of Tests.
VLSI Design
Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
1994 Misc conf
Sequential test generation with reduced test clocks for partial scan designs.
VTS
Soo Young Lee, Kewal K. Saluja
1993 J jnl
A Tutorial on Built-In Self-Test, Part 2: Applications.
IEEE Des. Test Comput.
Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
1993 J jnl
A Tutorial on Built-in Self-Test. I. Principles.
IEEE Des. Test Comput.
Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
1993 J jnl
An Efficient Algorithm for Sequential Circuit Test Generation.
IEEE Trans. Computers
Todd P. Kelsey, Kewal K. Saluja, Soo Young Lee
1993 J jnl
An efficient algorithm for bipartite PLA folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yeh Liu, Kewal K. Saluja
1993 Misc conf
CCSTG: an efficient test pattern generator for sequential circuits.
VTS
Kyuchull Kim, Kewal K. Saluja
1993 C conf
Efficient Test Vectors for ISCAS Sequential Benchmark Circuits.
ISCAS
Soo Young Lee, Kewal K. Saluja
1993 J jnl
Theory, Analysis and Implementation of an On-Line BIST Technique.
VLSI Design
Rajiv Sharma, Kewal K. Saluja
1992 Misc conf
An Efficient Method for Computation of Signatures.
VLSI Design
Chin-Foo See, Kewal K. Saluja
1992 J jnl
An Efficient Signature Computation Method.
IEEE Des. Test Comput.
Kewal K. Saluja, Chin-Foo See
1992 A conf
An algorithm to reduce test application time in full scan designs.
ICCAD
Soo Young Lee, Kewal K. Saluja
1992 — conf
Incorporating Testability Considerations in High-Level Systhesis.
FTCS
Ashutosh Mujumdar, Kewal K. Saluja, Rajiv Jain
1992 Misc conf
On fault deletion problem in concurrent fault simulation for synchronous sequential circuits.
VTS
Kyuchull Kim, Kewal K. Saluja
1992 Misc conf
Zero cost testing of check bits in RAMs with on-chip ECC.
VTS
Parameswaran Ramanathan, Kewal K. Saluja, Michael J. Franklin
1991 J jnl
A method of reducing aliasing in a built-in self-test environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Keiho Akiyama, Kewal K. Saluja
1991 A conf
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults.
ITC
Manoj Franklin, Kewal K. Saluja
1991 — conf
Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC.
FTCS
Manoj Franklin, Kewal K. Saluja
1990 J jnl
A built-in self-test algorithm for row/column pattern sensitive faults in RAMs.
IEEE J. Solid State Circuits
Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
1990 J jnl
Built-in Self-testing of Random-Access Memories.
Computer
Manoj Franklin, Kewal K. Saluja
1990 J jnl
Design and Analysis of a Gracefully Degrading Interleaved Memory System.
IEEE Trans. Computers
Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
1990 J jnl
Improved Test Generation for High-Activity Circuits.
IEEE Des. Test Comput.
Kewal K. Saluja, Kyuchull Kim
1989 — conf
A study of time-redundant fault tolerance techniques for high-performance pipelined computers.
FTCS
Gurindar S. Sohi, Manoj Franklin, Kewal K. Saluja
1989 A conf
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability.
ITC
Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
1989 A conf
Fast test generation for sequential circuits.
ICCAD
Todd P. Kelsey, Kewal K. Saluja
1989 — conf
Row/column pattern sensitive fault detection in RAMs via built-in self-test.
FTCS
Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita
1988 J jnl
A Data Compression Technique for Built-In Self-Test.
IEEE Trans. Computers
Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky
1988 J jnl
A concurrent testing technique for digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kewal K. Saluja, Rajiv Sharma, Charles R. Kime
1988 J jnl
A new approach to the design of built-in self-testing PLAs for high fault coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shambhu J. Upadhyaya, Kewal K. Saluja
1988 J jnl
An experimental study to determine task size for rollback recovery systems.
IEEE Trans. Computers
Shambhu J. Upadhyaya, Kewal K. Saluja
1988 — conf
An implementation and analysis of a concurrent built-in self-test technique.
FTCS
Rajiv Sharma, Kewal K. Saluja
1988 J jnl
Test Scheduling and Control for VLSI Built-In Self-Test.
IEEE Trans. Computers
Gary L. Craig, Charles R. Kime, Kewal K. Saluja
1987 A* conf
BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays.
DAC
Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya
1987 J jnl
Built-In Self-Testing RAM: A Practical Alternative.
IEEE Des. Test
Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita
1987 A* conf
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.
ISCA
Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan
1986 A conf
A Novel Approach for Testing Memories Using a Built-In Self Testing Technique.
ITC
Kim T. Le, Kewal K. Saluja
1986 J jnl
A Wachtdog Processor Based General Rollback Technique with Multiple Retries.
IEEE Trans. Software Eng.
Shambhu J. Upadhyaya, Kewal K. Saluja
1986 J jnl
An Alternative to Scan Design Methods for Sequential Machines.
IEEE Trans. Computers
Kewal K. Saluja, Ramaswami Dandapani
1986 J jnl
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.
IEEE Trans. Computers
Kozo Kinoshita, Kewal K. Saluja
1986 J jnl
Testable Design of Single-Output Sequential Machines Using Checking Experiments.
IEEE Trans. Computers
Kewal K. Saluja, Ramaswami Dandapani
1985 A conf
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.
ITC
Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita
1985 J jnl
Design of Programmable Logic Arrays for Parallel Testing.
Comput. Syst. Sci. Eng.
C. Boswell, Kewal K. Saluja, Kozo Kinoshita
1985 J jnl
Test Pattern Generation for API Faults in RAM.
IEEE Trans. Computers
Kewal K. Saluja, Kozo Kinoshita
1984 A conf
Built-in Testing of Memory Using On-chip Compact Testing Scheme.
ITC
Kozo Kinoshita, Kewal K. Saluja
1984 J jnl
Testable design of large random access memories.
Integr.
Kewal K. Saluja, Kim Thang Le
1983 A conf
A Simplified Algorithm for Testing Microprocessors.
ITC
Kewal K. Saluja, Li Shen, Stephen Y. H. Su
1983 J jnl
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.
IEEE Trans. Computers
Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara
1983 A conf
Testing Computer Hardware through Data Compression in Space and Time.
ITC
Kewal K. Saluja, Mark G. Karpovsky
1982 A* conf
An enhancement of lssd to reduce test pattern generation effort and increase fault coverage.
DAC
Kewal K. Saluja
1980 J jnl
Fault diagnosis in loop-connected systems.
Inf. Sci.
Kewal K. Saluja, Brian D. O. Anderson
1980 J jnl
Synchronous Sequential Machines: A Modular and Testable Design.
IEEE Trans. Computers
Kewal K. Saluja
1979 J jnl
Minimization of Reed-Muller Canonic Expansion.
IEEE Trans. Computers
Kewal K. Saluja, E. H. Ong
1975 J jnl
Fault Detecting Test Sets for Reed-Muller Canonic Networks.
IEEE Trans. Computers
Kewal K. Saluja, Sudhakar M. Reddy
1974 J jnl
Easily Testable Two-Dimensional Cellular Logic Arrays.
IEEE Trans. Computers
Kewal K. Saluja, Sudhakar M. Reddy
1974 J jnl
On Minimally Testable Logic Networks.
IEEE Trans. Computers
Kewal K. Saluja, Sudhakar M. Reddy
1972 — conf
Multiple Faults in Reed-Muller Canonic Networks
SWAT
Kewal K. Saluja, Sudhakar M. Reddy