Kevin Stawiasz

14 papers A 1Misc 2Journal 4Unranked 7

Year	Rank	Type	Title / Venue / Authors
2015	—	`conf`	Analyzing path delays for accelerated testing of logic chips. IRPS Emily Ray, Barry P. Linder, Raphael Robertazzi, Kevin Stawiasz, Alan J. Weger, Emmanuel Yashchin, James H. Stathis, Peilin Song
2015	—	`conf`	SOI FinFET soft error upset susceptibility and analysis. IRPS Phil Oldiges, Kenneth P. Rodbell, Michael S. Gordon, John G. Massey, Kevin Stawiasz, Conal E. Murray, Henry H. K. Tang, K. Kim, K. Paul Muller
2015	J	`jnl`	The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban
2014	—	`conf`	5.1 POWER8 ISSCC Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
2014	—	`conf`	5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 ISSCC Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich
2013	—	`conf`	Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators. ESSCIRC Jente B. Kuang, Keith A. Jenkins, Kevin Stawiasz, Jeremy D. Schaub
2011	J	`jnl`	A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS. IEEE J. Solid State Circuits Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan
2010	—	`conf`	A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS. ISSCC Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan
2008	J	`jnl`	A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. IEEE J. Solid State Circuits Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler
2007	J	`jnl`	A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou
2004	A	`conf`	Experimental measurement of a novel power gating structure with intermediate power saving mode. ISLPED Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz
2003	—	`conf`	Minimizing inductive noise in system-on-a-chip with multiple power gating structures. ESSCIRC Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, David F. Heidel, Michael Immediato
1998	Misc	`conf`	Designing a Testable System on a Chip. VTS Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz
1998	Misc	`conf`	High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz