Keren Zhu - RankMe

63 papers A* 5A 21B 3Journal 20Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM With Self-Assembled Bitcell Units and MILP-Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuyu Wang, Xinglong Yan, Zecheng Xu, Ke Hu, Keren Zhu, Shuo Li, Fan Yang, Xuan Zeng
2026	J	`jnl`	PigMap2: A Physical Information-Guided Technology Mapping Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cunqing Lan, Hongyang Pan, Zhiang Wang, Xuan Zeng, Fan Yang, Keren Zhu
2026	—	`conf`	PigMap3: A Physically Aware Incremental Mapping Framework with On-the-fly Post-Layout Critical Path Tracking. ASP-DAC Hongyang Pan, Cunqing Lan, Zhiang Wang, Xuan Zeng, Fan Yang, Keren Zhu
2025	A	`conf`	BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-LayoutSimulation. ICCAD Haoyang Sang, Changhao Yan, Zhaori Bi, Keren Zhu, Xuan Zeng
2025	A	`conf`	DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement. DATE Chuyu Wang, Ke Hu, Fan Yang, Keren Zhu, Xuan Zeng
2025	A*	`conf`	Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization. DAC Jintao Li, Haochang Zhi, Jiang Xiao, Keren Zhu, Yun Li
2025	A	`conf`	ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis. DATE Hongyang Pan, Keren Zhu, Fan Yang, Zhufei Chu, Xuan Zeng
2025	—	`conf`	HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. ISPD Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu
2025	A	`conf`	LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models. ICCAD Zhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025	A*	`conf`	MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing. DAC Wangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu, Zhaori Bi, Dian Zhou, Xuan Zeng
2025	A	`conf`	NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction. ICCAD Yuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
2025	J	`jnl`	PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peng Xu, Jindong Tu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu
2025	J	`jnl`	Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration. ACM Trans. Design Autom. Electr. Syst. Peng Xu, Su Zheng, Mingzi Wang, Ziyang Yu, Shixin Chen, Tinghuan Chen, Keren Zhu, Tsung-Yi Ho, Bei Yu
2025	J	`jnl`	Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis. ACM Trans. Design Autom. Electr. Syst. Hongyang Pan, Keren Zhu, Fan Yang, Xuan Zeng, Sen Liu, Yong Xiao, Yun Shao, Zhufei Chu
2025	A	`conf`	Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search. ICCAD Yiyang Zhao, Xuyang Zhao, Zhaori Bi, Ming Zhu, Qiwei Zhan, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2024	A	`conf`	A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing. DATE Souradip Poddar, Ahmet Faruk Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, David Z. Pan
2024	B	`conf`	A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). ASPDAC Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
2024	A	`conf`	AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. ICCAD Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024	J	`jnl`	AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. CoRR Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024	J	`jnl`	Erratum to: Large circuit models: opportunities and challenges. Sci. China Inf. Sci. Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	J	`jnl`	ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan
2024	B	`conf`	ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. ASPDAC Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan
2024	J	`jnl`	LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation. CoRR Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan
2024	J	`jnl`	Large circuit models: opportunities and challenges. Sci. China Inf. Sci. Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024	—	`conf`	Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu
2024	B	`conf`	Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). ASPDAC Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, Keren Zhu
2024	A*	`conf`	Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation. DAC Peng Xu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu
2024	A	`conf`	Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. ICCAD Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu
2024	J	`jnl`	Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. CoRR Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu
2024	A	`conf`	Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis. ICCAD Ruiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
2024	J	`jnl`	The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2023	A	`conf`	AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. ICCAD Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu
2023	J	`jnl`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2023	J	`jnl`	Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan
2023	A	`conf`	ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. DATE Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan
2023	—	`conf`	Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities. ISPD Ahmet Faruk Budak, Keren Zhu, Hao Chen, Souradip Poddar, Linran Zhao, Yaoyao Jia, David Z. Pan
2023	A	`conf`	Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. ICCAD Ahmet Faruk Budak, Keren Zhu, David Z. Pan
2023	J	`jnl`	Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. CoRR Ahmet Faruk Budak, Keren Zhu, David Z. Pan
2023	—	`conf`	Reinforcement Learning Guided Detailed Routing for Custom Circuits. ISPD Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren
2023	J	`jnl`	Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System. IEEE Trans. Circuits Syst. II Express Briefs Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan
2022	—	`conf`	AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. ISPD Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren
2022	—	`conf`	Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). ASP-DAC Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan
2022	A	`conf`	Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. ICCAD Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan
2022	J	`jnl`	Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. CoRR Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan
2022	—	`conf`	Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan
2022	—	`conf`	Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). ASP-DAC Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan
2022	J	`jnl`	TAG: Learning Circuit Spatial Embedding From Layouts. CoRR Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren
2022	A	`conf`	TAG: Learning Circuit Spatial Embedding from Layouts. ICCAD Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren
2021	—	`conf`	An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2021	—	`conf`	MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan
2021	J	`jnl`	MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan
2021	A	`conf`	OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan
2021	J	`jnl`	Optimizer Fusion: Efficient Training with Better Locality and Parallelism. CoRR Zixuan Jiang, Jiaqi Gu, Mingjie Liu, Keren Zhu, David Z. Pan
2021	A*	`conf`	Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	—	`conf`	An Efficient Training Framework for Reversible Neural Architectures. ECCV (27) Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu, David Z. Pan
2020	A*	`conf`	Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan
2020	A	`conf`	Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	—	`conf`	Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network. MLCAD Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, David Z. Pan
2020	—	`conf`	S ASP-DAC Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A	`conf`	Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan
2020	A	`conf`	Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A	`conf`	GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A	`conf`	MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan