Kentaroh Katoh

24 papers A 3B 1C 1Misc 1Journal 10Unranked 8
YearRankTypeTitle / Venue / Authors
2025 A conf
A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA.
DATE
Kentaroh Katoh, Toru Nakura, Haruo Kobayashi
2025 A conf
High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops.
ITC
Kentaroh Katoh, Toru Nakura, Haruo Kobayashi
2023 — conf
A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation.
ITC-Asia
Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2023 A conf
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion.
ITC
Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
2023 J jnl
Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing.
IEICE Electron. Express
Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
2022 — conf
High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST.
ATS
Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2022 Misc conf
Innovative Practices Track: Innovative Analog Circuit Testing Technologies.
VTS
Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2022 J jnl
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies.
J. Electron. Test.
Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2015 — conf
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement.
ISQED
Kentaroh Katoh, Kazuteru Namba
2015 J jnl
Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.
J. Electron. Test.
Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi
2014 J jnl
A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.
J. Electron. Test.
Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi
2014 J jnl
Analog/mixed-signal circuit design in nano CMOS era.
IEICE Electron. Express
Haruo Kobayashi, Hitoshi Aoki, Kentaroh Katoh, Congbing Li
2013 — conf
An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators.
Asian Test Symposium
Kentaroh Katoh, Yuta Doi, Satoshi Ito, Haruo Kobayashi, Ensi Li, Nobukazu Takai
2013 — conf
Digital Compensation for Timing Mismatches in Interleaved ADCs.
Asian Test Symposium
Ru Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh
2012 J jnl
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2010 — conf
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.
Asian Test Symposium
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2009 — conf
A Delay Measurement Technique Using Signature Registers.
Asian Test Symposium
Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito
2009 J jnl
Design for Delay Fault Testability of 2-Rail Logic Circuits.
IEICE Trans. Inf. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2009 J jnl
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.
IEICE Trans. Inf. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2008 J jnl
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.
Inf. Media Technol.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2008 J jnl
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.
IPSJ Trans. Syst. LSI Des. Methodol.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2007 — conf
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.
DFT
Abderrahim Doumar, Kentaroh Katoh, Hideo Ito
2006 B conf
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.
ETS
Kentaroh Katoh, Hideo Ito
2005 C conf
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.
IOLTS
Kentaroh Katoh, Abderrahim Doumar, Hideo Ito