Kensuke Iizuka

22 papers B 1C 1Journal 7Unranked 13
YearRankTypeTitle / Venue / Authors
2024 J jnl
Power Optimized Design Framework for FPGA Clusters.
IPSJ Trans. Syst. LSI Des. Methodol.
Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano
2024 C conf
Power analysis of an optical interconnected FPGA cluster for roadside units.
ICCE
Hideharu Amano, Kensuke Iizuka
2023 J jnl
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search.
IEICE Trans. Inf. Syst.
M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2023 — conf
Board Allocation Algorithm for the Resource Management System of FiC.
MCSoC
Takumi Inage, Kensuke Iizuka, Hideharu Amano
2023 J jnl
Parallel Implementation of CNN on Multi-FPGA Cluster.
IEICE Trans. Inf. Syst.
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
2023 — conf
Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster.
candar
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
2023 J jnl
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters.
IEICE Trans. Inf. Syst.
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
2022 — conf
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems.
MCSoC
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2022 — conf
Power Analysis of Directly-connected FPGA Clusters.
COOL CHIPS
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
2022 J jnl
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System.
IEICE Trans. Inf. Syst.
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
2022 — conf
Toward a training of CNNs on a multi-FPGA system.
CANDARW
Aoi Hiruma, Kensuke Iizuka, Hideharu Amano
2021 — conf
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System.
COOL CHIPS
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
2021 — conf
Implementing VTA, a tensor accelerator on Flow-in-Cloud.
ACIT
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2021 J jnl
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System.
IEICE Trans. Inf. Syst.
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2021 — conf
M-KUBOS/PYNQ Cluster for multi-access edge computing.
CANDAR
Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano
2021 — conf
Parallel Implementation of CNN on Multi-FPGA Cluster.
MCSoC
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
2021 J jnl
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud).
IEICE Trans. Inf. Syst.
Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano
2020 — conf
A Method of Partitioning Convolutional Layer to Multiple FPGAs.
ISOCC
Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano
2020 — conf
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system.
CANDAR (Workshops)
Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2020 — conf
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System.
CANDAR (Workshops)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2019 — conf
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation.
HEART
Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano
2019 B conf
Demonstration of Flow-in-Cloud: A Multi-FPGA System.
FPL
Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano