Kenshu Seto

30 papers A 2B 1C 1Journal 13Unranked 13
YearRankTypeTitle / Venue / Authors
2026 A conf
Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture.
FPGA
Ryo Iwasaki, Tatsuya Sasaki, Yumi Iseki, Sota Kohata, Miyu Yoshida, Kenshu Seto, Masahiro Iida
2025 — conf
Application of Nonvolatile IP with MTJ to eFPGA.
NVMSA
Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2025 — conf
Enhancing FPGA Routing Efficiency with Graph Neural Network-Based Congestion Prediction.
HEART
Kazuki Tokuishi, Motoki Amagasaki, Masato Kiyama, Kenshu Seto
2025 — conf
Minimizing Local Interconnections to Reduce Chip Area in eFPGAs.
HEART
Kenshu Seto, Masahiro Iida
2025 J jnl
Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP.
IPSJ Trans. Syst. LSI Des. Methodol.
Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2025 — conf
Proposal for Non-Volatilization of eFPGA Core.
COOL CHIPS
Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2025 J jnl
Scalar Replacement in the Presence of Multiple Write Accesses with Non-constant Reuse Distances.
IPSJ Trans. Syst. LSI Des. Methodol.
Kenshu Seto
2021 A conf
Scalar replacement in the presence of multiple write accesses for high-level synthesis.
DATE
Kenshu Seto
2020 J jnl
Shift Register Initialization in Scalar Replacement for Reducing Code Size.
IPSJ Trans. Syst. LSI Des. Methodol.
Kenshu Seto
2019 J jnl
Scalar Replacement with Circular Buffers.
IPSJ Trans. Syst. LSI Des. Methodol.
Kenshu Seto
2019 — conf
Small Memory Footprint Neural Network Accelerators.
ISQED
Kenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, Nikil D. Dutt
2018 J jnl
Scalar Replacement with Polyhedral Model.
IPSJ Trans. Syst. LSI Des. Methodol.
Kenshu Seto
2014 J jnl
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis.
Inf. Media Technol.
Shingo Kusakabe, Kenshu Seto
2014 J jnl
Forwarding Unit Generation for Loop Pipelining in High-level Synthesis.
IPSJ Trans. Syst. LSI Des. Methodol.
Shingo Kusakabe, Kenshu Seto
2013 J jnl
Loop Fusion with Outer Loop Shifting for High-level Synthesis.
Inf. Media Technol.
Yuta Kato, Kenshu Seto
2013 J jnl
Loop Fusion with Outer Loop Shifting for High-level Synthesis.
IPSJ Trans. Syst. LSI Des. Methodol.
Yuta Kato, Kenshu Seto
2010 J jnl
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands.
Inf. Media Technol.
Kenshu Seto, Masahiro Fujita
2010 J jnl
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands.
IPSJ Trans. Syst. LSI Des. Methodol.
Kenshu Seto, Masahiro Fujita
2009 J jnl
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2008 — conf
Custom Instruction Generation with High-Level Synthesis.
SASP
Kenshu Seto, Masahiro Fujita
2008 J jnl
Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.
J. Satisf. Boolean Model. Comput.
Masahiro Fujita, Kenshu Seto, Thanyapat Sakunkonchak
2008 B conf
SAT-based resource binding for reducing critical path delays.
FPL
Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki
2007 — conf
Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.
IESS
Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2007 — conf
Protocol Transducer Synthesis using Divide and Conquer approach.
ASP-DAC
Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita
2006 — conf
Dynamically reconfigurable protocol transducer.
FPT
Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2005 — conf
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.
FPT
Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2003 C conf
Engineering Changes in Field Modifiable Architectures.
MEMOCODE
Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita
2003 — conf
Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.
HICSS
Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima
2002 — conf
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.
IWLS
Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
2002 — conf
Field modifiable architecture with FPGAs and its design methodology.
FPT
Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita