Kenneth D. Wagner

13 papers A* 1A 4Journal 8
YearRankTypeTitle / Venue / Authors
2005 J jnl
Keeping current with silicon and systems technology in the mid-90s.
IEEE Des. Test Comput.
Kenneth D. Wagner
1999 J jnl
Robust Scan-Based Logic Test in VDSM Technologies.
Computer
Kenneth D. Wagner
1998 J jnl
Design for Testability Techniques at the Behavioral and Register-Transfer Levels.
J. Electron. Test.
Sujit Dey, Anand Raghunathan, Kenneth D. Wagner
1996 J jnl
EIC Message.
IEEE Des. Test Comput.
Kenneth D. Wagner, Yervant Zorian
1996 A* conf
High-Level Synthesis for Testability: A Survey and Perspective.
DAC
Kenneth D. Wagner, Sujit Dey
1993 A conf
Testable Programmable Digital Clock Pulse Control Elements.
ITC
Kenneth D. Wagner, Bernd Könemann
1991 A conf
Enhancing Board Functional Self-Test by Concurrent Sampling.
ITC
Kenneth D. Wagner, Thomas W. Williams
1990 J jnl
Guest Editorial: The Many Faces of Test.
IEEE Des. Test Comput.
Kenneth D. Wagner
1988 J jnl
Clock system design.
IEEE Des. Test
Kenneth D. Wagner
1988 A conf
Design for Testability of Mixed Signal Integrated Circuits.
ITC
Kenneth D. Wagner, Thomas W. Williams
1988 J jnl
Probability models for pseudorandom test sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Edward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner
1987 J jnl
Pseudorandom Testing.
IEEE Trans. Computers
Kenneth D. Wagner, Cary K. Chin, Edward J. McCluskey
1985 A conf
The Error Latency of Delay Faults in Combinational and Sequential Circuits.
ITC
Kenneth D. Wagner