Kenji Tsuchida

12 papers Journal 5Unranked 7

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	A perspective on NVRAM technology for future computing system. VLSI-DAT Katsuhiko Hoya, Kosuke Hatsuda, Kenji Tsuchida, Yohji Watanabe, Yusuke Shirota, Tatsunori Kanai
2017	—	`conf`	23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. ISSCC KwangMyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh
2010	—	`conf`	A 64Mb MRAM with clamped-reference and adequate-reference schemes. ISSCC Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe
2008	—	`conf`	A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory. DFT Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi
2006	—	`conf`	A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ISSCC Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, Masahiko Nakayama, Shuichi Tahara, Hiroaki Yoda
2006	—	`conf`	MRAM Write Error Categorization with QCKB. MTDT Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa
2003	—	`conf`	Resistance ratio read (R CICC Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda
1992	J	`jnl`	Word-line architecture for highly reliable 64-Mb DRAM. IEEE J. Solid State Circuits Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi
1991	J	`jnl`	A 33-ns 64-Mb DRAM. IEEE J. Solid State Circuits Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka
1990	J	`jnl`	The stabilized reference-line (SRL) technique for scaled DRAMs. IEEE J. Solid State Circuits Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka
1989	J	`jnl`	An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka
1989	J	`jnl`	New nibbled-page architecture for high-density DRAMs. IEEE J. Solid State Circuits Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi