Kenji Shimazaki

14 papers Journal 5Unranked 9
YearRankTypeTitle / Venue / Authors
2010 J jnl
Gate Delay Estimation in STA under Dynamic Power Supply Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto
2010 — conf
Gate delay estimation in STA under dynamic power supply noise.
ASP-DAC
Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto
2009 — conf
A minimum decap allocation technique based on simultaneous switching for nanoscale SoC.
CICC
Kenji Shimazaki, Takaaki Okumura
2006 J jnl
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs.
IEICE Trans. Electron.
Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa
2005 — conf
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs.
CICC
Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa
2005 J jnl
Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits.
IEICE Trans. Electron.
Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa
2005 J jnl
Power-Supply Noise Reduction with Design for Manufacturability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroyuki Tsujikawa, Kenji Shimazaki, Shozo Hirano, Kazuhiro Sato, Masanori Hirofuji, Junichi Shimada, Mitsumi Ito, Kiyohito Mukai
2005 — conf
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.
CICC
Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata
2004 — conf
Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement.
CICC
Shen Lin, Makoto Nagata, Kenji Shimazaki, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang
2003 J jnl
A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroyuki Tsujikawa, Shozo Hirano, Kenji Shimazaki
2003 — conf
A substrate noise analysis methodology for large-scale mixed-signal ICs.
CICC
Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto
2002 — conf
A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification.
CICC
Hiroyulu Tsujikawa, Kenji Shimazaki, Shozo Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno
2002 — conf
An EMI-Noise Analysis on LSI Design with Impedance Estimation.
ISQED
Kenji Shimazaki, Shouzou Hirano, Hiroyuki Tsujikawa
2000 — conf
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator.
ISQED
Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano