Kenji Noda - RankMe

13 papers A 2B 1Journal 6Unranked 4

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2010	J	`jnl`	A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2009	A	`conf`	A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
2008	B	`conf`	A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2008	A	`conf`	Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2008	—	`conf`	Session 16 - Embedded memory. CICC Kenji Noda, Jean-Christophe Vial
2001	—	`conf`	A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina
2001	J	`jnl`	An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. IEEE J. Solid State Circuits Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi
2000	J	`jnl`	A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. IEEE J. Solid State Circuits Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi
2000	—	`conf`	An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. CICC Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi
1998	—	`conf`	A High-Level Synthesis Method for Weakly Testable Data Paths. Asian Test Symposium Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara
1997	J	`jnl`	A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. IEEE J. Solid State Circuits Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto
1990	J	`jnl`	A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. IEEE J. Solid State Circuits Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama