Kenji Kurishima

12 papers Journal 11Unranked 1
YearRankTypeTitle / Venue / Authors
2019 J jnl
InGaP/GaAsSb/InGaAsSb double heterojunction bipolar transistors with 703-GHz
IEICE Electron. Express
Takuya Hoshi, Norihide Kashio, Yuta Shiratori, Kenji Kurishima, Minoru Ida, Hideaki Matsuzaki
2016 J jnl
An InP-Based 27-GHz-Bandwidth Limiting TIA IC Designed to Suppress Undershoot and Ringing in Its Output Waveform.
IEICE Trans. Electron.
Hiroyuki Fukuyama, Michihiro Hirata, Kenji Kurishima, Minoru Ida, Masami Tokumitsu, Shogo Yamanaka, Munehiko Nagatani, Toshihiro Itoh, Kimikazu Sano, Hideyuki Nosaka, Koichi Murata
2016 J jnl
Type-II InGaAsSb-Base Double Heterojunction Bipolar Transistors Simultaneously Exhibiting over 600-GHz
IEICE Trans. Electron.
Norihide Kashio, Takuya Hoshi, Kenji Kurishima, Minoru Ida, Hideaki Matsuzaki
2012 J jnl
A low-power wideband InP-HBT 2
IEICE Electron. Express
Yves Bouvier, Kimikazu Sano, Munehiko Nagatani, Koichi Murata, Kenji Kurishima, Minoru Ida
2012 J jnl
Performance of InP/InGaAs HBTs with a Thin Highly
IEICE Trans. Electron.
Kenji Kurishima, Minoru Ida, Norihide Kashio, Yoshino K. Fukai
2009 J jnl
Emitter-metal-related degradation in InP-based HBTs operating at high current density and its suppression by refractory metal.
Microelectron. Reliab.
Yoshino K. Fukai, Kenji Kurishima, Norihide Kashio, Minoru Ida, Shoji Yamahata, Takatomo Enoki
2008 J jnl
Highly Reliable Submicron InP-Based HBTs with over 300-GHz
IEICE Trans. Electron.
Norihide Kashio, Kenji Kurishima, Yoshino K. Fukai, Shoji Yamahata
2005 J jnl
A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation.
IEICE Trans. Electron.
Hideyuki Nosaka, Makoto Nakamura, Kimikazu Sano, Minoru Ida, Kenji Kurishima, Tsugumichi Shibata, Masami Tokumitsu, Masahiro Muraguchi
2005 J jnl
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki
2004 J jnl
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.
IEEE J. Solid State Circuits
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi
2004 — conf
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop].
ESSCIRC
Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata
2002 J jnl
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors.
IEEE J. Solid State Circuits
Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki