Kenji Kise - RankMe

86 papers A* 1A 3B 5C 2Misc 10Journal 25Unranked 40

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	CFU Proving Ground: a Hardware/Software Co-Design Framework for Leveraging a Custom Function Unit and RISC-V Custom Instructions. MCSoC Aoba Fujino, Kenji Kise
2025	—	`conf`	Design and Implementation of a High-Performance RISC-V SoC for FPGAs with Linux Support. MCSoC Yuki Yagi, Kenji Kise
2025	—	`conf`	Robbit: A User-Friendly and Two-Wheeled Self-Balancing Robot Using an FPGA. MCSoC Daichi Kumagai, Komei Kodera, Yuya Iwata, Kenji Kise
2024	A	`ed.`	Proceedings of the 38th ACM International Conference on Supercomputing, ICS 2024, Kyoto, Japan, June 4-7, 2024 ICS Kenji Kise, Valentina Salapura, Murali Annavaram, Ana Lucia Varbanescu
2023	—	`conf`	A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs. MCSoC Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise
2023	J	`jnl`	An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration. IEEE Access Fumio Hamanaka, Takashi Odan, Kenji Kise, Thiem Van Chu
2023	—	`conf`	An open-source and GUI-capable RISC-V computer system on a low-end FPGA board. MCSoC Kenji Kise
2023	—	`conf`	Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators. HEART Md. Ashraful Islam, Kenji Kise
2022	J	`jnl`	An Efficient Resource Shared RISC-V Multicore Architecture. IEICE Trans. Inf. Syst. Md. Ashraful Islam, Kenji Kise
2022	J	`jnl`	RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor. IEICE Trans. Inf. Syst. Takuto Kanamori, Takashi Odan, Kazuki Hirohata, Kenji Kise
2021	—	`conf`	A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA. MCSoC Fumio Hamanaka, Takuto Kanamori, Kenji Kise
2021	—	`conf`	A function-rich FPGA system of camera image processing for video meeting. MCSoC Takashi Odan, Takuto Kanamori, Kenji Kise
2021	—	`conf`	Efficient Resource Shared RISC-V Multicore Processor. MCSoC Md. Ashraful Islam, Kenji Kise
2021	—	`conf`	RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions. MCSoC Takuto Kanamori, Kenji Kise
2020	J	`jnl`	A portable and Linux capable RISC-V computer system in Verilog HDL. CoRR Junya Miura, Hiromu Miyazaki, Kenji Kise
2020	A	`conf`	Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs. FPGA Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka
2020	J	`jnl`	High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter. IEICE Trans. Inf. Syst. Elsayed A. Elsayed, Kenji Kise
2020	J	`jnl`	RVCoreP : An optimized RISC-V soft processor of five-stage pipelining. CoRR Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise
2020	J	`jnl`	RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions. CoRR Takuto Kanamori, Hiromu Miyazaki, Kenji Kise
2020	J	`jnl`	RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors. CoRR Md. Ashraful Islam, Hiromu Miyazaki, Kenji Kise
2020	J	`jnl`	RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining. IEICE Trans. Inf. Syst. Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise
2019	—	`conf`	An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA. MCSoC Katsunoshin Matsui, Md. Ashraful Islam, Kenji Kise
2019	—	`conf`	An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA. HEART Hiromu Miyazaki, Junya Miura, Kenji Kise
2019	J	`jnl`	LEF: An Effective Routing Algorithm for Two-Dimensional Meshes. IEICE Trans. Inf. Syst. Thiem Van Chu, Kenji Kise
2019	—	`conf`	Towards an Efficient Hardware Architecture for Odd-Even Based Merge Sorter. MCSoC Elsayed A. Elsayed, Kenji Kise
2018	Misc	`conf`	A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath. FCCM Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise
2018	B	`conf`	An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs. FPL Thiem Van Chu, Kenji Kise
2018	—	`conf`	An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem. MCSoC Yuuma Azuma, Hayato Sakagami, Kenji Kise
2018	J	`jnl`	ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment. IEICE Trans. Inf. Syst. Shimpei Sato, Ryohei Kobayashi, Kenji Kise
2018	—	`conf`	Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records. MCSoC Elsayed A. Elsayed, Kenji Kise
2018	—	`conf`	Swap Based Merge Network for High Performance Sorting Accelerators. HEART Kenji Kise
2018	—	`conf`	Very Massive Hardware Merge Sorter. FPT Makoto Saitoh, Kenji Kise
2017	J	`jnl`	A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism. IEICE Trans. Inf. Syst. Ryohei Kobayashi, Kenji Kise
2017	—	`conf`	Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip. MCSoC Thiem Van Chu, Myeonggu Kang, Shi Fa, Kenji Kise
2017	J	`jnl`	Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. ACM Trans. Reconfigurable Technol. Syst. Thiem Van Chu, Shimpei Sato, Kenji Kise
2017	Misc	`conf`	High-Performance Hardware Merge Sorter. FCCM Susumu Mashimo, Thiem Van Chu, Kenji Kise
2016	—	`conf`	A Cost-Effective and Scalable Merge Sorter Tree on FPGAs. CANDAR Takuma Usui, Thiem Van Chu, Kenji Kise
2016	J	`jnl`	A High-speed Verilog HDL Simulation Method using a Lightweight Translator. SIGARCH Comput. Archit. News Ryohei Kobayashi, Tomohiro Misono, Kenji Kise
2016	—	`conf`	An Effective Page Padding Method for RAM Buffer Algorithms to Enhance the SSD Endurance. CANDAR Eri Ogawa, Kenji Kise
2016	J	`jnl`	Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. SIGARCH Comput. Archit. News Susumu Mashimo, Thiem Van Chu, Kenji Kise
2016	—	`conf`	The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
2015	—	`conf`	A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors. CANDAR Yuki Matsuda, Ryosuke Sasakawa, Kenji Kise
2015	—	`conf`	A Challenge of Portable and High-Speed FPGA Accelerator. ARC Takuma Usui, Ryohei Kobayashi, Kenji Kise
2015	—	`conf`	ArchHDL: A Novel Hardware RTL Design Environment in C++. ARC Shimpei Sato, Kenji Kise
2015	—	`conf`	Dependable real-time task execution scheme for a many-core platform. DFTS Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise
2015	—	`conf`	Effective Parallel Simulation of ArchHDL under Manycore Environment. CANDAR Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, Kenji Kise
2015	Misc	`conf`	Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. FCCM Thiem Van Chu, Shimpei Sato, Kenji Kise
2015	—	`conf`	FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems. MCSoC Ryohei Kobayashi, Kenji Kise
2015	—	`conf`	Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research. MCSoC Eri Ogawa, Yuki Matsuda, Tomohiro Misono, Ryohei Kobayashi, Kenji Kise
2015	B	`conf`	Ultra-fast NoC emulation on a single FPGA. FPL Thiem Van Chu, Shimpei Sato, Kenji Kise
2015	J	`jnl`	Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs. IEICE Trans. Inf. Syst. Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, Kenji Kise
2014	—	`conf`	A framework for efficient rapid prototyping by virtually enlarging FPGA resources. ReConFig Shinya Takamaeda-Yamazaki, Kenji Kise
2014	—	`conf`	An NoC-based evaluation platform for safety-critical automotive applications. APCCAS Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
2014	—	`conf`	Design and Performance Evaluation of a Manycore Processor for Large FPGA. MCSoC Haruka Mori, Kenji Kise
2014	—	`conf`	KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. MCSoC Thiem Van Chu, Shimpei Sato, Kenji Kise
2014	B	`conf`	Ultrasmall: The smallest MIPS soft processor. FPL Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise
2014	B	`conf`	flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. FPL Shinya Takamaeda-Yamazaki, Kenji Kise
2013	B	`conf`	Application Aware DRAM Bank Partitioning in CMP. ICPADS Takakazu Ikeda, Kenji Kise
2013	—	`conf`	LEF: long edge first routing for two-dimensional mesh network on chip. NoCArc@MICRO Ryosuke Sasakawa, Kenji Kise
2013	J	`jnl`	The Ultrasmall soft processor. SIGARCH Comput. Archit. News Yuichiro Tanaka, Shimpei Sato, Kenji Kise
2012	—	`conf`	CoreSymphony architecture. Conf. Computing Frontiers Tomoyuki Nagatsuka, Yoshito Sakaguchi, Kenji Kise
2012	—	`conf`	ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. ARC Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise
2012	Misc	`conf`	Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations. ICNC Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise
2011	Misc	`conf`	A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors. ICNC Naoki Fujieda, Kenji Kise
2011	J	`jnl`	An FPGA-based scalable simulation accelerator for tile architectures. SIGARCH Comput. Archit. News Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise
2011	J	`jnl`	CoreSymphony: an efficient reconfigurable multi-core architecture. SIGARCH Comput. Archit. News Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, Kenji Kise
2011	—	`conf`	Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. ISOCC Mochamad Asri, Naoki Fujieda, Kenji Kise
2010	Misc	`conf`	CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. ICNC Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga
2010	Misc	`conf`	Pattern-Based Systematic Task Mapping for Many-Core Processors. ICNC Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
2010	Misc	`conf`	Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
2009	C	`conf`	A Study of an Infrastructure for Research and Development of Many-Core Processors. PDCAT Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
2009	J	`jnl`	SimCell: A Processor Simulator for Multi-Core Architecture Research. Inf. Media Technol. Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise
2009	C	`conf`	The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors. PDCAT Yosuke Mori, Kenji Kise
2007	J	`jnl`	Introduction. SIGARCH Comput. Archit. News Kenji Kise, Toshinori Sato, Hironori Nakajo
2006	J	`jnl`	ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software. Parallel Comput. Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
2006	J	`jnl`	ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility. Parallel Comput. Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
2006	—	`conf`	Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment. VECPAR Satoshi Ohshima, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba
2005	J	`jnl`	A time-to-live based reservation algorithm on fully decentralized resource discovery in Grid computing. Parallel Comput. Sanya Tangpongprasit, Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
2005	Misc	`conf`	Evaluation of the Acknowledgment Reduction in a Software-DSM System. PPAM Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba
2005	A*	`conf`	Towards scalable and simple software-DSM systems. SOSP Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba
2004	—	`conf`	Effect of auto-tuning with user's knowledge for numerical software. Conf. Computing Frontiers Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
2004	Misc	`conf`	The SimCore/Alpha Functional Simulator. WCAE Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba
2003	—	`conf`	FIBER: A Generalized Framework for Auto-tuning Software. ISHPC Takahiro Katagiri, Kenji Kise, Hiroaki Honda, Toshitsugu Yuba
2003	—	`conf`	SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator. Asia-Pacific Computer Systems Architecture Conference Kenji Kise, Hiroki Honda, Toshitsugu Yuba
2002	A	`conf`	DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations. IPDPS Ryo Takata, Kenji Kise, Hiroki Honda, Toshitsugu Yuba
1996	J	`jnl`	An efficient algorithm for the euclidean distance transformation. Syst. Comput. Jpn. Toshihiro Kato, Tomio Hirata, Toyofumi Saito, Kenji Kise