Kenji Anami - RankMe

14 papers Journal 14

Year	Rank	Type	Title / Venue / Authors
2005	J	`jnl`	A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
1996	J	`jnl`	A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. IEEE J. Solid State Circuits Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami
1993	J	`jnl`	A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. IEEE J. Solid State Circuits Toru Shiomi, Tomohisa Wada, Shigeki Ohbayashi, Atsushi Ohba, Hiroki Honda, Yoshiyuki Ishigaki, Shiro Hine, Kenji Anami, Kimio Suzuki, Tadashi Sumi
1993	J	`jnl`	A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's. IEEE J. Solid State Circuits Motomu Ukita, Shuji Murakami, Tadato Yamagata, Hirotada Kuriyama, Yasumasa Nishimura, Kenji Anami
1991	J	`jnl`	A 21-mW 4-Mb CMOS SRAM for battery operation. IEEE J. Solid State Circuits Shuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami
1991	J	`jnl`	A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy. IEEE J. Solid State Circuits Atsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, Shimpei Kayano
1991	J	`jnl`	An 8 ns 4 Mb serial access memory. IEEE J. Solid State Circuits Hirotada Kuriyama, Toshihiko Hirose, Shuji Murakami, Tomohisa Wada, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami
1991	J	`jnl`	Variable bit organization as a new test function for standard memories. IEEE J. Solid State Circuits Tomohisa Wada, Masanao Eino, Motomu Ukita, Kenji Anami
1990	J	`jnl`	A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture. IEEE J. Solid State Circuits Toshihiko Hirose, Hirotada Kuriyama, Shuji Murakami, Kojiro Yuzuriha, Takao Mukai, Kazuhito Tsutsumi, Yasumasa Nishimura, Yoshio Kohno, Kenji Anami
1990	J	`jnl`	Simple noise model and low-noise data-output buffer for ultrahigh-speed memories. IEEE J. Solid State Circuits Tomohisa Wada, Masanao Eino, Kenji Anami
1989	J	`jnl`	Improvement of soft-error rate in MOS SRAMs. IEEE J. Solid State Circuits Shuji Murakami, Katsuki Ichinose, Kenji Anami, Shimpei Kayano
1988	J	`jnl`	A macro analysis of soft errors in static RAMs. IEEE J. Solid State Circuits Yasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano