Kenichi Osada - RankMe

29 papers A 2C 1Journal 11Unranked 15

Year	Rank	Type	Title / Venue / Authors
2015	—	`conf`	A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. OFC Takashi Takemoto, Yasunobu Matsuoka, Yoshikazu Sugiyama, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Etsuko Nomoto, Kouji Nakahara, Hideo Arimoto, Kenichi Osada, Tatemi Ido
2013	—	`conf`	Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. ISQED Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai
2012	C	`conf`	Fully digital voltage-mode control based on predictive hysteresis method (FDVC-PH) for DC-DC converters. ISCAS Ming Liu, Tatsuo Nakagawa, Kenichi Osada
2012	A	`conf`	Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors. IROS Kiyoto Ito, Makoto Saen, Kenichi Osada
2011	—	`conf`	6 Tbps/W, 1 Tbps/mm 3DIC Futoshi Furuta, Kenichi Osada
2011	J	`jnl`	Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
2011	A	`ed.`	Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011 ISLPED Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino
2010	J	`jnl`	3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda
2010	—	`conf`	Development of a CAD tool for 3D-FPGAs. 3DIC Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi
2010	—	`conf`	Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno
2010	J	`jnl`	Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
2009	—	`conf`	A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
2009	—	`conf`	An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda
2008	—	`conf`	65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
2008	—	`conf`	A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
2008	J	`jnl`	Memory at VLSI Circuits Symposium. IEEE J. Solid State Circuits Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi
2007	—	`conf`	A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
2007	—	`conf`	Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. ISSCC Makoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie
2005	J	`jnl`	A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J. Solid State Circuits Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada
2005	J	`jnl`	A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh
2005	—	`conf`	Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. CICC Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa
2004	J	`jnl`	0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi
2004	—	`conf`	Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara
2004	—	`conf`	Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara
2004	—	`conf`	Reviews and future prospects of low-voltage embedded RAMs. CICC Kiyoo Itoh, Kenichi Osada, Takayda Kawahara
2004	J	`jnl`	SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. IEEE J. Solid State Circuits Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara
2003	J	`jnl`	16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. IEEE J. Solid State Circuits Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi
2001	J	`jnl`	Universal-V IEEE J. Solid State Circuits Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi
1996	J	`jnl`	A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure