Kenichi Okada - RankMe

284 papers A 1B 1C 7Journal 131Unranked 144

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	27.6 A 9.7GHz Self-Linearized-VCO-Based FMCW Chirp Generator Achieving 1.56GHz/μs Slope and 0.57μS Duration with 0.094% RMS Frequency Error. ISSCC Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Michele Rossoni, Wenqian Wang, Ashbir Aviat Fadila, Duo Li, Minzhe Tang, Dongfan Xu, Carrel de Gomez, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi Okada
2026	J	`jnl`	A 142-164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE. IEEE J. Solid State Circuits Yudai Yamazaki, Yohei Morishita, Sunghwan Park, Takaya Uchino, Chenxin Liu, Jun Sakamaki, Akihiro Egami, Ryosuke Hasaba, Ken Takahashi, Tomoki Abe, Tomohiro Murata, Yoichi Nakagawa, Takashi Tomura, Hiroshi Taneda, Kei Murayama, Makoto Tsukahara, Hiroko Ota, Yoko Nakabayashi, Ryuji Kinugawa, Takumi Kojima, Anyi Tian, Kotaro Ito, Chun Wang, Hans Herdian, Yi Zhang, Zheng Li, Wenqian Wang, Hongye Huang, Dingxin Xu, Sena Kato, Michihiro Ide, Shinsuke Hara, Issei Watanabe, Akifumi Kasamatsu, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Koji Takinami, Kenichi Okada
2026	J	`jnl`	A 52 Gb/s 8.9-dBm EIRP 300-GHz-Band Amplifier-Last Outphasing Transmitter With Path Mismatch Calibration in 65-nm CMOS. IEEE J. Solid State Circuits Chun Wang, Olivia Angel Yong, Hans Herdian, Wenqian Wang, Abanob Shehata, Carrel da Gomez, Chenxin Liu, Yudai Yamazaki, Kazuaki Kunihiro, Hiroyuki Sakai, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada
2026	J	`jnl`	A Power-Efficient K-Band Circular Polarized 256-Element CMOS Phased-Array Transmitter With Coupler-End Structure for LEO Satellite Terminal. IEEE J. Solid State Circuits Xiaolin Wang, Dongwon You, Xi Fu, Takeshi Ota, Michihiro Ide, Sena Kato, Jill C. Mayeda, Makoto Higaki, Jumpei Sudo, Hiroshi Takizawa, Masashi Shirakura, Takashi Tomura, Hiroyuki Sakai, Kazuaki Kunihiro, Kenichi Okada, Atsushi Shirane
2025	—	`conf`	11.1 A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite Constellations. ISSCC Sena Kato, Jill C. Mayeda, Keito Yuasa, Michihiro Ide, Takeshi Ota, Shu Date, Yudai Yamazaki, Xiaolin Wang, Xi Fu, Dongwon You, Makoto Higaki, Jumpei Sudo, Hiroshi Takizawa, Masashi Shirakura, Takashi Tomura, Hiroyuki Sakai, Kazuaki Kunihiro, Kenichi Okada, Atsushi Shirane
2025	—	`conf`	5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM. ISSCC Yuncheng Zhang, Zezheng Liu, Duo Li, Minzhe Tang, Yi Zhang, Hongye Huang, Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation. IEEE Access Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications. IEEE Solid State Circuits Lett. Michihiro Ide, Keito Yuasa, Sena Kato, Shu Date, Takashi Tomura, Kenichi Okada, Atsushi Shirane
2025	J	`jnl`	A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112-170 GHz for 6G Transceivers. IEEE Solid State Circuits Lett. Chenxin Liu, Yudai Yamazaki, Anyi Tian, Chun Wang, Hans Herdian, Abanob Shehata, Han Nie, Minzhe Tang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A 2.5 dB noise figure 28 GHz current-reused noise-cancelling LNA with g IEICE Electron. Express Yi Zhang, Minzhe Tang, Dongfan Xu, Jian Pang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025	—	`conf`	A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate. ASP-DAC Yi Zhang, Minzhe Tang, Zheng Li, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement. IEEE Solid State Circuits Lett. Yuibi Gomi, Akira Sato, Waleed Madany, Kenichi Okada, Satoshi Adachi, Masatoshi Itoh, Masanori Hashimoto
2025	J	`jnl`	A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. IEEE J. Solid State Circuits Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada
2025	—	`conf`	A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter. CICC Daxu Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset. IEEE J. Solid State Circuits Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Minzhe Tang, Dingxin Xu, Shinsuke Hara, Akifumi Kasamatsu, Takashi Tomura, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A Compact D-Band Phase Shifter With 0.1-Degree Phase Resolution and Ultra-Low Phase Error in 65-nm CMOS. IEEE J. Solid State Circuits Takaya Uchino, Yudai Yamazaki, Anyi Tian, Chenxin Liu, Sunghwan Park, Abanob Shehata, Sena Kato, Takumi Kojima, Haruto Tanaka, Masayuki Kikuchi, Jill C. Mayeda, Ryuji Kinugawa, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025	—	`conf`	A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO. ASP-DAC Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur. IEEE J. Solid State Circuits Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	A LEO Satellite Mounted 256-Element 19 GHz CMOS Phased-Array Transmitter With On-Chip Amplitude and Phase Monitor. IEEE Access Xiaolin Wang, Dongwon You, Xi Fu, Gao Yuan, Takeshi Ota, Jill C. Mayeda, Jun Sakamaki, Ashbir Aviat Fadila, Makoto Higaki, Jumpei Sudo, Hiroshi Takizawa, Masashi Shirakura, Takashi Tomura, Hiroyuki Sakai, Kazuaki Kunihiro, Kenichi Okada, Atsushi Shirane
2025	—	`conf`	A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NR. ASP-DAC Dongfan Xu, Minzhe Tang, Yi Zhang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator. IEEE J. Solid State Circuits Yuncheng Zhang, Zezheng Liu, Duo Li, Minzhe Tang, Yi Zhang, Hongye Huang, Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2025	J	`jnl`	Experimental Testbed for Frequency-Division Multiplexed Joint Radar-Communication System Validation in D-Band Using a 65-nm CMOS Communication Transceiver. IEEE Access Carrel da Gomez, Chenxin Liu, Hans Herdian, Hiroyuki Sakai, Kazuaki Kunihiro, Kenichi Okada
2025	J	`jnl`	Millimeter-Wave Wirelessly-Powered Phased-Array Relay Transceiver Utilizing CMOS Switching Rectifier-Type Mixer. IEICE Trans. Electron. Sena Kato, Keito Yuasa, Michihiro Ide, Kenichi Okada, Atsushi Shirane
2025	—	`conf`	Millimeter-wave GaAs Rectifier with Differential Signal 4:1 Power Combiner for Simultaneous Wireless Information and Power Transmission. LASCAS Masayuki Kikuchi, Michihiro Ide, Jill C. Mayeda, Sena Kato, Keito Yuasa, Kenichi Okada, Atsushi Shirane
2025	J	`jnl`	NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers. IEEE Access Hongye Huang, Ashbir Aviat Fadila, Dingxin Xu, Waleed Madany, Wenqian Wang, Zezheng Liu, Yuang Xiong, Tianshi Hu, Bangan Liu, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada
2024	—	`conf`	10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. ISSCC Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada
2024	—	`conf`	24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS. ISSCC Chun Wang, Hans Herdian, Wenbin Zheng, Chenxin Liu, Jill C. Mayeda, Yuxuan Liu, Olivia Angel Yong, Wenqian Wang, Yuncheng Zhang, Carrel da Gomez, Abanob Shehata, Sena Kato, Ibrahim Abdo, Teruo Jyo, Hiroshi Hamada, Hiroyuki Takahashi, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2024	—	`conf`	300-GHz-Band InP HBT Power Amplifier and InP-CMOS Hybrid Phased-Array Transmitter. BCICTS Teruo Jyo, Ibrahim Abdo, Hiroshi Hamada, Munehiko Nagatani, Adam Pander, Hitoshi Wakita, Miwa Mutoh, Yuta Shiratori, Daisuke Kitayama, Carrel da Gomez, Chun Wang, Kota Hatano, Chenxin Liu, Ashbir Aviat Fadila, Jian Pang, Atsushi Shirane, Kenichi Okada, Hiroyuki Takahashi
2024	—	`conf`	35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers. A-SSCC Abanob Shehata, Hans Herdian, Chun Wang, Chenxin Liu, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2024	C	`conf`	A 24-71-GHz Tri-Mode Mixer Using Harmonic Selection for Multi-Band 5G NR. ISCAS Dongfan Xu, Minzhe Tang, Yi Zhang, Zheng Li, Atsushi Shirane, Kenichi Okada
2024	—	`conf`	A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond. VLSI Technology and Circuits Yi Zhang, Minzhe Tang, Jian Pang, Zheng Li, Dongfan Xu, Dingxin Xu, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2024	—	`conf`	A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer. VLSI Technology and Circuits Sena Kato, Shu Date, Tao Ruoxin, Yasuto Narukiyo, Hiroki Hayashi, Keito Yuasa, Michihiro Ide, Takashi Tomura, Kenichi Okada, Atsushi Shirane
2024	—	`conf`	A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset. VLSI Technology and Circuits Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2024	—	`conf`	A Compact D-Band Phase Shifter with 0.1-degree Phase Resolution and 0.8-degree RMS Phase Error in 65 nm CMOS. A-SSCC Takaya Uchino, Yudai Yamazaki, Sunghwan Park, Chenxin Liu, Anyi Tian, Abanob Shehata, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2024	J	`jnl`	A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation. IEEE J. Solid State Circuits Xi Fu, Dongwon You, Yun Wang, Xiaolin Wang, Ashbir Aviat Fadila, Chenxin Liu, Sena Kato, Chun Wang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada
2024	C	`conf`	A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases. ISCAS Sidharth Thomas, Jaskirat Singh Virdi, Anshul Verma, Bishnu Prasad Das, Kenichi Okada, Pratap Narayan Singh
2024	J	`jnl`	A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression. IEEE J. Solid State Circuits Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Jill C. Mayeda, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang, Jian Pang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2024	J	`jnl`	A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. IEEE J. Solid State Circuits Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada
2024	J	`jnl`	A synthesizable spread spectrum clock generator based on type-II/III fractional- IEICE Electron. Express Waleed Madany, Hongye Huang, Bangan Liu, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Junjun Qiu, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada
2024	J	`jnl`	Design of Synthesizable Digital Phase Locked Loops. IPSJ Trans. Syst. LSI Des. Methodol. Yuncheng Zhang, Kenichi Okada
2024	J	`jnl`	Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium. IEEE J. Solid State Circuits Kenichi Okada
2024	J	`jnl`	Millimeter-Wave Transceiver Utilizing On-Chip Butler Matrix for Simultaneous 5G Relay Communication and Wireless Power Transfer. IEICE Trans. Electron. Keito Yuasa, Michihiro Ide, Sena Kato, Kenichi Okada, Atsushi Shirane
2024	C	`conf`	Sub-THz CMOS Phased-Array Transceiver Design for 6G. ISCAS Kenichi Okada
2023	—	`conf`	A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation. ISSCC Xi Fu, Dongwon You, Xiaolin Wang, Michihiro Ide, Yuncheng Zhang, Jun Sakamaki, Ashbir Aviat Fadila, Zheng Li, Yun Wang, Jumpei Sudo, Makoto Higaki, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane
2023	—	`conf`	A 24-49-GHz CMOS Area-Efficient Phase-Invariant Mixed-Type Attenuator With Capacitive Compensation for 5G New Radio. ESSCIRC Zheng Li, Peng Luo, Jian Pang, Qiaoyu Wang, Atsushi Shirane, Kenichi Okada
2023	J	`jnl`	A 28GHz High-Accuracy Phase and Amplitude Detection Circuit for Dual-Polarized Phased-Array Calibration. IEICE Trans. Electron. Yudai Yamazaki, Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada
2023	—	`conf`	A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. ISSCC Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada
2023	J	`jnl`	A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD. IEEE J. Solid State Circuits Yudai Yamazaki, Jun Sakamaki, Jian Pang, Joshua Alvin, Zheng Li, Dongwon You, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada
2023	J	`jnl`	A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station. IEEE J. Solid State Circuits Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Yun Wang, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Jeehoon Park, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2023	J	`jnl`	A 41-GHz 19.4-dBm P IEICE Electron. Express Zheng Li, Zixin Chen, Qiaoyu Wang, Junqing Liu, Jian Pang, Atsushi Shirane, Kenichi Okada
2023	—	`conf`	A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. CICC Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada
2023	—	`conf`	A 60-GHz Transformer-Based Power Amplifier Supporting 5G n263-band Applications. ICICDT Junqing Liu, Zheng Li, Minghao Fan, Yilun Chen, Atsushi Shirane, Kenichi Okada
2023	—	`conf`	A Dual-Mode Bi-Directional CMOS Mixer Using Push-Push Doubler for 300GHz-Band Transceivers. ESSCIRC Chenxin Liu, Ibrahim Abdo, Chun Wang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2023	—	`conf`	A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path. ESSCIRC Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Atsushi Shirane, Kenichi Okada
2023	J	`jnl`	A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount. IEEE Access Dongwon You, Xiaolin Wang, Hans Herdian, Xi Fu, Hojun Lee, Michihiro Ide, Carrel da Gomez, Zheng Li, Jill C. Mayeda, Daisuke Awaji, Jian Pang, Hiraku Sakamoto, Kenichi Okada, Atsushi Shirane
2023	J	`jnl`	A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations. IEEE J. Solid State Circuits Xi Fu, Dongwon You, Xiaolin Wang, Yun Wang, Carolyn Jill Mayeda, Yuan Gao, Michihiro Ide, Yuncheng Zhang, Jun Sakamaki, Ashbir Aviat Fadila, Zheng Li, Jumpei Sudo, Makoto Higaki, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane
2023	—	`conf`	A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler. ISSCC Dongwon You, Xi Fu, Xiaolin Wang, Yuan Gao, Wenqian Wang, Jun Sakamaki, Hans Herdian, Sena Kato, Michihiro Ide, Yuncheng Zhang, Ashbir Aviat Fadila, Zheng Li, Chun Wang, Yun Wang, Jumpei Sudo, Makoto Higaki, Nahoka Kawaguchi, Masaya Nitta, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane
2023	—	`conf`	A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression. VLSI Technology and Circuits Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang, Jian Pang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada
2023	—	`conf`	A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. VLSI Technology and Circuits Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	A 0.37mm IEICE Trans. Electron. Yuncheng Zhang, Bangan Liu, Teruki Someya, Rui Wu, Junjun Qiu, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	A 1.8-67GHz Divide-by-4 ILFD Using Area-Efficient Transformer-Based Injection-Enhancing Technique. ESSCIRC Yudai Yamazaki, Jian Pang, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	A 220-294 GHz Power Amplifier with 10-dBm Psat and 2.2% PAE in 250-nm InP DHBT. BCICTS Teruo Jyo, Hiroshi Hamada, Munehiko Nagatani, Hitoshi Wakita, Ibrahim Abdo, Miwa Mutoh, Yuta Shiratori, Kenichi Okada, Atsushi Shirane, Hiroyuki Takahashi
2022	—	`conf`	A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer. VLSI Technology and Circuits Michihiro Ide, Yuasa Keito, Sena Kato, Dongwon You, Ashbir Aviat Fadila, Jian Pang, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer. IEEE J. Solid State Circuits Michihiro Ide, Atsushi Shirane, Kiyoshi Yanagisawa, Dongwon You, Jian Pang, Kenichi Okada
2022	—	`conf`	A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio. ESSCIRC Minzhe Tang, Yi Zhang, Jian Pang, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation. ISSCC Xi Fu, Yun Wang, Dongwon You, Xiaolin Wang, Ashbir Aviat Fadila, Yi Zhang, Sena Kato, Chun Wang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station. VLSI Technology and Circuits Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Zhengyan Guo, Yun Wang, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	A 41-GHz 19.4-dBm PSATCMOS Doherty Power Amplifier for 5G NR Applications. ICTA Zheng Li, Zixin Chen, Qiaoyu Wang, Jian Pang, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. IEEE J. Solid State Circuits Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay Transceivers. ESSCIRC Sena Kato, Keito Yuasa, Michihiro Ide, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	A Compact and High-Resolution CMOS Switch-Type Phase Shifter Achieving 0.4-dB RMS Gain Error for 5G n260 Band. IEICE Trans. Electron. Jian Pang, Xueting Luo, Zheng Li, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. IEEE J. Solid State Circuits Yun Wang, Dongwon You, Xi Fu, Takeshi Nakamura, Ashbir Aviat Fadila, Teruki Someya, Atsuhiro Kawaguchi, Junjun Qiu, Jian Pang, Kiyoshi Yanagisawa, Bangan Liu, Yuncheng Zhang, Haosheng Zhang, Rui Wu, Shunichiro Masaki, Daisuke Yamazaki, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR. ISSCC Jian Pang, Yi Zhang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR. IEEE J. Solid State Circuits Yi Zhang, Jian Pang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	A low-power digital baseband circuit for GMSK demodulation in sub-GHz application. IEICE Electron. Express Junjun Qiu, Bangan Liu, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	An 8.5-dB Insertion Loss and 0.8° RMS Phase Error Ka-Band CMOS Hybrid Phase Shifter Featuring Nonuniform Matching for Satellite Communication. IEICE Trans. Electron. Xi Fu, Yun Wang, Xiaolin Wang, Xiaofan Gu, Xueting Luo, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada
2022	J	`jnl`	F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power. IEICE Trans. Electron. Ibrahim Abdo, Korkut Kaan Tokgoz, Atsushi Shirane, Kenichi Okada
2022	—	`conf`	Maximizing Energy Efficiency in Sub-THz Radio Communication and Prospective toward 6G. BCICTS Kenichi Okada
2022	B	`conf`	Millimeter-Wave CMOS Phased-Array Transceivers for 5G and Beyond. PIMRC Kenichi Okada, Jian Pang, Atsushi Shirane, Zheng Li, Yi Zhang, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro
2022	J	`jnl`	Performance Evaluation of Classification and Verification with Quadrant IQ Transition Image. IEICE Trans. Commun. Hiro Tamura, Kiyoshi Yanagisawa, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS. ISSCC Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver. ASP-DAC Yi Zhang, Jian Pang, Kiyoshi Yanagizawa, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. ISSCC Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Atsushi Shirane, Kenichi Okada
2021	J	`jnl`	64QAM wireless link with 300GHz InP-CMOS hybrid transceiver. IEICE Electron. Express Ibrahim Abdo, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A 0.25 mm ESSCIRC Zheng Sun, Dingxin Xu, Junjun Qiu, Zezheng Liu, Yuncheng Zhang, Hongye Huang, Hanli Liu, Bangan Liu, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver. ASP-DAC Ibrahim Abdo, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Atsushi Shirane, Kenichi Okada
2021	J	`jnl`	A 0.85mm IEEE Trans. Circuits Syst. I Regul. Pap. Zheng Sun, Hanli Liu, Hongye Huang, Dexian Tang, Dingxin Xu, Tohru Kaneko, Zheng Li, Jian Pang, Rui Wu, Wei Deng, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter with 24-GHz Wireless Power and LO Transfer. VLSI Circuits Michihiro Ide, Atsushi Shirane, Kiyoshi Yanagisawa, Dongwon You, Jian Pang, Kenichi Okada
2021	—	`conf`	A 28GHz Bi-direction Transceiver with Temperature Compensation. ICTA Yi Zhang, Jian Pang, Zheng Li, Atsushi Shirane, Kenichi Okada
2021	J	`jnl`	A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. IEEE J. Solid State Circuits Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Jian Pang, Hanli Liu, Masaya Miyahara, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A 39GHz Divide-by-8 LC-Ring ILFD Designed for 5G New Radio n260 Band. ICTA Yudai Yamazaki, Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada
2021	J	`jnl`	A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. IEEE J. Solid State Circuits Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yuncheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A DSM-based Polar Transmitter with 23.8% System Efficiency. ASP-DAC Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation. VLSI Circuits Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Weichu Chen, Yun Wang, Dongwon You, Zheng Sun, Yuncheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada
2021	J	`jnl`	A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Aravind Tharayil Narayanan, Haosheng Zhang, Teruki Someya, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System. ASP-DAC Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate. ESSDERC Hans Herdian, Takeshi Inoue, Takuichi Hirano, Masatsugu Sogabe, Atsushi Shirane, Kenichi Okada
2020	J	`jnl`	300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers. IEEE J. Solid State Circuits Hiroshi Hamada, Takuya Tsutsumi, Hideaki Matsuzaki, Takuya Fujimura, Ibrahim Abdo, Atsushi Shirane, Kenichi Okada, Go Itami, Ho-Jin Song, Hiroki Sugiyama, Hideyuki Nosaka
2020	—	`conf`	A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. VLSI Circuits Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yucheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada
2020	J	`jnl`	A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. IEEE J. Solid State Circuits Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Bangan Liu, Aravind Tharayil Narayanan, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada
2020	J	`jnl`	A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio. IEICE Trans. Electron. Jian Pang, Ryo Kubozoe, Zheng Li, Masaru Kawabuchi, Atsushi Shirane, Kenichi Okada
2020	—	`conf`	A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. ASP-DAC Zheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Joshua Alvin, Bangan Liu, Zheng Sun, Hongye Huang, Atsushi Shirane, Kenichi Okada
2020	—	`conf`	A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. VLSI Circuits Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Kiyoshi Yanagisawa, Junjun Qiu, Yun Wang, Jian Pang, Atsushi Shirane, Kenichi Okada
2020	J	`jnl`	A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS. IEEE J. Solid State Circuits Yun Wang, Rui Wu, Jian Pang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Xi Fu, Daiki Matsumoto, Takeshi Nakamura, Ryo Kubozoe, Masaru Kawabuchi, Bangan Liu, Haosheng Zhang, Junjun Qiu, Hanli Liu, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada
2020	—	`conf`	A Compact 37-40GHz CMOS Switch-Type Phase Shifter with Fine-Tuning Stage Achieving 0.4-dB RMS Gain Error. ICTA Jian Pang, Xueting Luo, Zheng Li, Atsushi Shirane, Kenichi Okada
2020	J	`jnl`	A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. IEICE Trans. Electron. Zheng Sun, Dingxin Xu, Hongye Huang, Zheng Li, Hanli Liu, Bangan Liu, Jian Pang, Teruki Someya, Atsushi Shirane, Kenichi Okada
2020	—	`conf`	Millimeter-Wave CMOS Phased-Array Transceiver Supporting Dual-Polarized MIMO for 5G NR. CICC Kenichi Okada, Jian Pang
2020	—	`conf`	Wireless Devices Identification with Light-Weight Convolutional Neural Network Operating on Quadrant IQ Transition Image. NEWCAS Hiro Tamura, Kiyoshi Yanagisawa, Atsushi Shirane, Kenichi Okada
2019	—	`conf`	0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. VLSI Circuits Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Yun Wang, Atsushi Shirane, Kenichi Okada
2019	—	`conf`	300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology. BCICTS Hiroshi Hamada, Takuya Tsutsumi, Go Itami, Hiroki Sugiyama, Hideaki Matsuzaki, Kenichi Okada, Hideyuki Nosaka
2019	J	`jnl`	A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya
2019	—	`conf`	A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada
2019	J	`jnl`	A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio. IEEE J. Solid State Circuits Jian Pang, Rui Wu, Yun Wang, Masato Dome, Hisashi Kato, Hongye Huang, Aravind Tharayil Narayanan, Hanli Liu, Bangan Liu, Takeshi Nakamura, Takuya Fujimura, Masaru Kawabuchi, Ryo Kubozoe, Tsuyoshi Miura, Daiki Matsumoto, Zheng Li, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada
2019	—	`conf`	A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. ISSCC Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Aravind Tharayil Narayanan, Bangan Liu, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada
2019	J	`jnl`	A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. IEEE J. Solid State Circuits Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada
2019	J	`jnl`	A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. IEEE J. Solid State Circuits Yun Wang, Bangan Liu, Rui Wu, Hanli Liu, Aravind Tharayil Narayanan, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sung Tae Choi, Kenichi Okada, Akira Matsuzawa
2019	J	`jnl`	A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock. IEICE Trans. Electron. Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Rui Wu, Atsushi Shirane, Kenichi Okada
2019	J	`jnl`	A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM. IEICE Trans. Electron. Aravind Tharayil Narayanan, Kenichi Okada
2019	—	`conf`	An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada
2019	—	`conf`	An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
2019	—	`conf`	Millimeter-Wave CMOS Phased-Array Transceiver Toward 1Tbps Wireless Communication. BCICTS Kenichi Okada
2019	C	`conf`	Millimeter-Wave CMOS Transceiver Toward 1Tbps Wireless Communication. ISCAS Korkut Kaan Tokgoz, Kenichi Okada
2019	J	`jnl`	Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2019	J	`jnl`	ULPAC: A Miniaturized Ultralow-Power Atomic Clock. IEEE J. Solid State Circuits Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shigeyoshi Goka, Shinya Yanagimachi, Kenichi Okada
2019	—	`conf`	Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10 ISSCC Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shinya Yanagimachi, Kenichi Okada
2018	—	`conf`	A 0.85mm ESSCIRC Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, Kenichi Okada
2018	—	`conf`	A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. ISSCC Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. ISSCC Korkut Kaan Tokgoz, Shotaro Maki, Jian Pang, Noriaki Nagashima, Ibrahim Abdo, Seitaro Kawai, Takuya Fujimura, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay. A-SSCC Jian Pang, Korkut Kaan Tokgoz, Shotaro Maki, Zheng Li, Xueting Luo, Ibrahim Abdo, Seitarou Kawai, Hanli Liu, Bangan Liu, Makihiko Katsuragi, Kento Kimura, Atsushi Shirane, Kenichi Okada
2018	—	`conf`	A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. VLSI Circuits Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. IEEE J. Solid State Circuits Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada
2018	J	`jnl`	A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. IEICE Trans. Electron. Bangan Liu, Yun Wang, Jian Pang, Haosheng Zhang, Dongsheng Yang, Aravind Tharayil Narayanan, Dae Young Lee, Sung Tae Choi, Rui Wu, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. IEEE J. Solid State Circuits Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada
2018	—	`conf`	An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. ISSCC Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS. IEICE Electron. Express Korkut Kaan Tokgoz, Seitaro Kawai, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	Foreword. IEICE Trans. Electron. Kenichi Okada
2017	—	`conf`	24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. ISSCC Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS. IEICE Trans. Electron. Yun Wang, Makihiko Katsuragi, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	Analysis of Effective Material Properties of Metal Dummy Fills in a CMOS Chip. IEICE Trans. Commun. Takuichi Hirano, Ning Li, Kenichi Okada
2017	—	`conf`	Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	W-band ultra-high data-rate 65nm CMOS wireless transceiver. ASP-DAC Korkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	13.3 A 56Gb/s W-band CMOS wireless transceiver. ISSCC Korkut Kaan Tokgoz, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Jun Emmei, Masato Dome, Hisashi Kato, Jian Pang, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Yuuki Seo, Kimsrun Lim, Shinji Sato, Ning Li, Kengo Nakata, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 0.0055mm IEICE Trans. Electron. Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. IEEE J. Solid State Circuits Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. ASP-DAC Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. A-SSCC Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	F3: Radio architectures and circuits towards 5G. ISSCC Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic
2016	—	`conf`	Session 26 overview: Wireless for IoE. ISSCC Kenichi Okada, Jan van Sinderen
2016	J	`jnl`	Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	14.1 A 0.048mm ISSCC Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	19.5 An HCI-healing 60GHz CMOS transceiver. ISSCC Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 28-Gb/s 60-GHz wireless transceiver in 65nm CMOS with 64QAM capability. ASICON Kenichi Okada
2015	—	`conf`	A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. IEICE Trans. Electron. Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. ESSCIRC Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A tail-current modulated VCO with adaptive-bias scheme. ASP-DAC Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	An AM-PM Noise Mitigation Technique in Class-C VCO. IEICE Trans. Electron. Kento Kimura, Aravind Tharayil Narayanan, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Electron. Korkut Kaan Tokgoz, Kimsrun Lim, Seitarou Kawai, Nurul Fajri, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	Digitally Assisted Analog and RF Circuits. IEICE Trans. Electron. Kenichi Okada
2015	J	`jnl`	Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Angelo Nagari, Kenichi Okada, Marian Verhelst
2015	J	`jnl`	Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynänen, Kenichi Okada, Jaeha Kim
2015	—	`conf`	Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process. ESSDERC Ning Li, Takeshi Inoue, Takuichi Hirano, Jian Pang, Rui Wu, Kenichi Okada, Hitoshi Sakane, Akira Matsuzawa
2014	—	`conf`	15.1 A 0.0066mm ISSCC Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. ISSCC Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa
2014	—	`conf`	22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. ISSCC Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A 0.011 mm A-SSCC Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A 0.015-mm A-SSCC Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. IEEE J. Solid State Circuits Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation. IEICE Trans. Electron. Rui Wu, Yuuki Tsukui, Ryo Minami, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. ESSCIRC Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	F4: Mm-Wave advances for active safety and communication systems. ISSCC Marc Tiebout, Brian A. Floyd, Mike Keaveney, Pierre Busson, Kenichi Okada
2013	—	`conf`	A 0.022mm ISSCC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. ESSCIRC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. IEICE Trans. Electron. Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A 60 GHz up-conversion mixer using asymmetric layout with -41.1 dBc LO leakage. LASCAS Yuki Tsukui, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate. IEICE Electron. Express Hamid Kiumarsi, Hiroyuki Ito, Kenichi Okada, Yusuke Uemichi, Yasuto Chiba, Noboru Ishihara, Kazuya Masu
2013	J	`jnl`	A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs. IEICE Trans. Electron. Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. IEEE J. Solid State Circuits Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. ASP-DAC Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A full 4-channel 60 GHz direct-conversion transceiver. ASP-DAC Seitaro Kawai, Ryo Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Yuki Tsukui, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. ASP-DAC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. IEEE J. Solid State Circuits Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. IEEE J. Solid State Circuits Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
2013	—	`conf`	Session 13 overview: High-performance wireless. ISSCC Brian A. Floyd, Kenichi Okada
2012	J	`jnl`	A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. IEICE Trans. Electron. Wei Deng, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. ESSCIRC Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. ASP-DAC Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	A Dual-Conduction Class-C VCO for a Low Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Okada, You Nomiyama, Rui Murakami, Akira Matsuzawa
2012	—	`conf`	A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. ASP-DAC Wei Deng, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios. ASP-DAC Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	A Wideband Common-Gate Low-Noise Amplifier Using Capacitive Feedback. IEICE Trans. Electron. Toshihiko Ito, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. ISSCC Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
2012	J	`jnl`	Clock/Frequency Generation Circuits and Systems. J. Electr. Comput. Eng. Woogeun Rhee, Antonio Liscidini, Jae-Yoon Sim, Kenichi Okada, Sudhakar Pamarti
2012	J	`jnl`	Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Electron. Qinghong Bu, Ning Li, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	Inter-Stage Tunable Notch Filter for a Multi-Band WCDMA Receiver. IEICE Trans. Electron. Toshihiko Ito, Masaki Kanemaru, Satoshi Furuya, Dong Ta Ngoc Huy, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning. IEICE Trans. Electron. Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	A 14.3% PAE parallel class-A and AB 60GHz CMOS PA. IEICE Electron. Express Ning Li, Kota Matsushita, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing. A-SSCC Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. ASP-DAC Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. IEEE J. Solid State Circuits Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa
2011	—	`conf`	A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS. A-SSCC Hiroki Asada, Keigo Bunsen, Kota Matsushita, Rui Murakami, Qinghong Bu, Ahmed Musa, Takahiro Sato, Tatsuya Yamaguchi, Ryo Minami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. ISSCC Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa
2011	—	`conf`	A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver. ASICON Kenichi Okada
2011	—	`conf`	A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver. ISOCC Kenichi Okada
2011	J	`jnl`	A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications. IEEE J. Solid State Circuits Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Rui Ito, Takahiro Sekiguchi, Mototsugu Hamada, Kenichi Okada
2011	J	`jnl`	A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers. J. Electr. Comput. Eng. Yusaku Ito, Kenichi Okada, Kazuya Masu
2011	—	`conf`	A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. ESSCIRC Wei Deng, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A new figure of Merit of LC oscilators considering frequency tuning range. ASICON Takahiro Sato, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	An ultra-compact LC-VCO using a stacked-spiral inductor. IEICE Electron. Express Rui Murakami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. ASP-DAC Wei Deng, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate. IEICE Trans. Electron. Yuya Ono, Takuichi Hirano, Kenichi Okada, Jiro Hirokawa, Makoto Ando
2011	J	`jnl`	Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip. IEICE Trans. Electron. Ryo Minami, Jee Young Hong, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving. IEICE Trans. Electron. Ning Li, Qinghong Bu, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	Tunable CMOS Power Amplifiers for Reconfigurable Transceivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa
2010	—	`conf`	A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. ASP-DAC Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa
2010	—	`conf`	A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. ESSCIRC Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
2010	—	`conf`	A 60GHz direct-conversion transmitter in 65nm CMOS technology. ASP-DAC Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling. IEICE Trans. Electron. Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Keigo Bunsen, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider. IEICE Trans. Electron. Shoichi Hara, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators. IEICE Trans. Electron. Rui Murakami, Shoichi Hara, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ning Li, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shoichi Hara, Rui Murakami, Kenichi Okada, Akira Matsuzawa
2009	J	`jnl`	Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Takeshi Ito, Kenichi Okada, Kazuya Masu
2009	J	`jnl`	Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hirotaka Sugawara, Kenichi Okada, Kazuya Masu
2008	J	`jnl`	A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. IEEE J. Solid State Circuits Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu
2008	—	`conf`	A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. ASP-DAC Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa
2008	J	`jnl`	Analysis of CMOS Transconductance Amplifiers for Sampling Mixers. IEICE Trans. Electron. Ning Li, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2008	C	`conf`	Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. ISCAS Shoichi Hara, Takeshi Ito, Kenichi Okada, Akira Matsuzawa
2008	—	`conf`	LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. ASP-DAC Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu
2008	J	`jnl`	Physical Modeling of MEMS Variable Inductor. IEEE Trans. Circuits Syst. II Express Briefs Tackya Yammouch, Kenichi Okada, Kazuya Masu
2008	J	`jnl`	Reconfigurable RF CMOS Circuit for Cognitive Radio. IEICE Trans. Commun. Kazuya Masu, Kenichi Okada
2008	—	`conf`	Small-area CMOS RF distributed mixer using multi-port inductors. ASP-DAC Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2008	J	`jnl`	Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators. IEICE Trans. Electron. Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2007	—	`conf`	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu
2007	—	`conf`	A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu
2007	—	`conf`	A Wideband CMOS LC-VCO Using Variable Inductor. ASP-DAC Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu
2007	—	`conf`	Adaptable wire-length distribution with tunable occupation probability. SLIP Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu
2007	—	`conf`	Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. ASP-DAC Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu
2006	—	`conf`	Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. PATMOS Kenichi Okada, Takumi Uezono, Kazuya Masu
2006	J	`jnl`	RF Passive Components Using Metal Line on Si CMOS. IEICE Trans. Electron. Kazuya Masu, Kenichi Okada, Hiroyuki Ito
2006	C	`conf`	Reconfigurable CMOS low noise amplifier for self compensation. ISCAS D. Kawazoe, Hirotaka Sugawara, Tatsuya Ito, Kenichi Okada, Kazuya Masu
2006	J	`jnl`	Statistical Modeling of a Via Distribution for Yield Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Uezono, Kenichi Okada, Kazuya Masu
2006	—	`conf`	Via Distribution Model for Yield Estimation. ISQED Takumi Uezono, Kenichi Okada, Kazuya Masu
2005	—	`conf`	A dynamic reconfigurable RF circuit architecture. ASP-DAC Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu
2005	J	`jnl`	Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
2005	J	`jnl`	Evaluation of X Architecture Using Interconnect Length Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu
2005	—	`conf`	Evaluation of on-chip transmission line interconnect using wire length distribution. ASP-DAC Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu
2005	—	`conf`	Prediction of delay time for future LSI using on-chip transmission line interconnects. SLIP Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu
2005	J	`jnl`	Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2005	—	`conf`	Wire Length Distribution Model Considering Core Utilization for System on Chip. ISVLSI Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
2005	J	`jnl`	Wire Length Distribution Model for System LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
2004	—	`conf`	Differential transmission line interconnect for high speed and low power global wiring. CICC Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2004	—	`conf`	High speed and low power on-chip micro network circuit with differential transmission line. SoC Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Kazuya Masu
2004	J	`jnl`	Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. IEICE Electron. Express Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2004	A	`conf`	ULSI Interconnect Length Distribution Model Considering Core Utilization. DATE Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
2003	—	`conf`	A statistical gate delay model for intra-chip and inter-chip variabilities. ASP-DAC Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera
2003	J	`jnl`	Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Okada, Hidetoshi Onodera
2003	J	`jnl`	Statistical Gate-Delay Modeling with Intra-Gate Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera
2003	—	`conf`	Statistical modeling of gate-delay variation with consideration of intra-gate variability. ISCAS (5) Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera
2000	C	`conf`	Statistical modeling of device characteristics with systematic fluctuation. ISCAS Kenichi Okada, Hidetoshi Onodera