Ken Takeuchi - RankMe

157 papers A 3C 12Journal 70Unranked 71

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	ReRAM Resistance Design of LRS and HRS for Ultrahigh-Capacity Digital Memory and Analog Computation-in-Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chihiro Matsui, Ayumu Yamada, Naoko Misawa, Ken Takeuchi
2025	J	`jnl`	4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation. CoRR Fuyuki Kihara, Seiji Uenohara, Satoshi Awamura, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025	—	`conf`	Bayesian Neural Network Realization by Random Telegraph Noise in 40nm TaOX ReRAM CiM. IMW Junnosuke Furukawa, Koki Shibata, Kenshin Yamauchi, Naoko Misawa, Satoshi Awamura, Chihiro Matsui, Ken Takeuchi
2025	—	`conf`	Conductance Variation-Assisted Adversarial Attack Robustness on 40nm TaOx-based ReRAM CiM. IRPS Kenshin Yamauchi, Naoko Misawa, Satoshi Awamura, Masahiro Morimoto, Chihiro Matsui, Ken Takeuchi
2025	—	`conf`	Hybrid ReRAM-NMC & SRAM-CiM Matrix Multiplication for Large Language Model. COOL CHIPS Tao Wang, Daqi Lin, Kenshin Yamauchi, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025	J	`jnl`	RGB-Event Multi-Modal NV-CiM to Detect Object by Mapping-Oriented Enhanced-Feature Pyramid Network with Mapping-Aware Group Convolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuya Ichikawa, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025	—	`conf`	Read Voltage Dependency of Random Telegraph Noise in the Intermediate State of TaOx-based ReRAM. IRPS Kenshin Yamauchi, Naoko Misawa, Hisashi Shima, Yasuhisa Naitoh, Hiroyuki Akinaga, Chihiro Matsui, Ken Takeuchi
2025	J	`jnl`	Signed Approximate Adder Tree and Quantization- and Bit-Pruning-Aware Training for Digital Computation-in-Memory. IEICE Trans. Electron. Daqi Lin, Tao Wang, Adil Padiyal, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2025	—	`conf`	Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices. ASP-DAC Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi
2025	C	`conf`	VaLI: Variability-aware Fine-tuning with Low-rank Adapter and Iterative Training for ReRAM Computation-in-Memory. ISCAS Tao Wang, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2024	J	`jnl`	3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing. IEICE Trans. Electron. Fuyuki Kihara, Chihiro Matsui, Ken Takeuchi
2024	J	`jnl`	Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern Classifier. IEICE Trans. Electron. Ayumu Yamada, Zhiyuan Huang, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2024	—	`conf`	Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers. IMW Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi
2024	J	`jnl`	FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. IEEE Trans. Very Large Scale Integr. Syst. Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
2024	J	`jnl`	Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Ken Takeuchi, Tetsuya Iizuka, Kazuko Nishimura, Jerald Yoo
2024	J	`jnl`	REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night. IEICE Trans. Electron. Yuya Ichikawa, Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023	—	`conf`	Analog Computation-in-Memory (CiM) for AI Applications. ICICDT Ken Takeuchi
2023	—	`conf`	Foreword. A-SSCC Ken Takeuchi
2023	J	`jnl`	Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chihiro Matsui, Ken Takeuchi
2023	A	`conf`	LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory. ICCAD Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023	—	`conf`	Neuromorphic Computation-in-Memory System (Invited). IRPS Ken Takeuchi
2023	—	`conf`	ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset. IRPS Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023	—	`conf`	Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance. IMW Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2023	J	`jnl`	Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM. IEICE Trans. Electron. Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi
2022	C	`conf`	Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing. ISCAS Naoko Misawa, Kenta Taoka, Chihiro Matsui, Ken Takeuchi
2022	C	`conf`	Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation. ISCAS Shinsei Yoshikiyo, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
2022	—	`conf`	Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation. IMW Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi
2022	—	`conf`	Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM. IMW Yuya Ichikawa, Akira Goda, Chihiro Matsui, Ken Takeuchi
2022	C	`conf`	Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing. ISCAS Chihiro Matsui, Eitaro Kobayashi, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
2021	C	`conf`	BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads. ISCAS Mamoru Fukuchi, Shun Suzuki, Kyosuke Maeda, Chihiro Matsui, Ken Takeuchi
2021	—	`conf`	Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing. VLSI Circuits Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
2021	C	`conf`	Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory. ISCAS Daiki Kojima, Ken Takeuchi
2021	—	`conf`	SE1: What Technologies Will Shape the Future of Computing? ISSCC Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag
2021	—	`conf`	Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory. IMW Kenta Taoka, Naoko Misawa, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi
2020	J	`jnl`	Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs). IEICE Trans. Electron. Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi
2020	J	`jnl`	Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Ken Takeuchi, Brian P. Ginsburg
2020	J	`jnl`	Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing. IEEE J. Solid State Circuits Shun Suzuki, Hiroki Aihara, Ken Takeuchi
2020	—	`conf`	Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers. VLSI-DAT Yoshiki Kakuta, Reika Kinoshita, Hiroshi Kinoshita, Chihiro Matsui, Ken Takeuchi
2020	J	`jnl`	System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs. IEICE Trans. Electron. Mamoru Fukuchi, Chihiro Matsui, Ken Takeuchi
2020	—	`conf`	Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance. ASP-DAC Reika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi
2019	J	`jnl`	3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition. IEEE J. Solid State Circuits Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi
2019	J	`jnl`	Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories. IEEE J. Solid State Circuits Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
2019	—	`conf`	Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime Extension. IRPS Kyoji Mizoguchi, Kyosuke Maeda, Ken Takeuchi
2019	—	`conf`	Comprehensive Analysis of Data-Retention and Endurance Trade-Off of 40nm TaOx-based ReRAM. IRPS Shouhei Fukuyama, Atsuna Hayakawa, Ryutaro Yasuhara, Shinpei Matsuda, Hiroshi Kinoshita, Ken Takeuchi
2019	—	`conf`	Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories. ASP-DAC Chihiro Matsui, Ken Takeuchi
2019	J	`jnl`	Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. Chihiro Matsui, Ken Takeuchi
2019	J	`jnl`	Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Ken Chang, Ken Takeuchi
2019	—	`conf`	Parallel Product-Sum Operation Neuromorphic Systems with 4-bit Ferroelectric FET Synapses. ESSDERC Koki Kamimura, Susumu Nohmi, Kenta Suzuki, Ken Takeuchi
2019	—	`conf`	Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing. A-SSCC Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi
2019	C	`conf`	Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories. ISCAS Chihiro Matsui, Ken Takeuchi
2019	J	`jnl`	Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. Integr. Chihiro Matsui, Ken Takeuchi
2019	—	`conf`	Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa
2018	C	`conf`	20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD. ISCAS Mamoru Fukuchi, Yukiya Sakaki, Chihiro Matsui, Ken Takeuchi
2018	C	`conf`	3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage. ISCAS Chihiro Matsui, Ken Takeuchi
2018	—	`conf`	9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories. CICC Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
2018	—	`conf`	A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD. A-SSCC Kota Tsurumi, Kenta Suzuki, Ken Takeuchi
2018	J	`jnl`	Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size. IEICE Trans. Electron. Hirofumi Takishita, Yutaka Adachi, Chihiro Matsui, Ken Takeuchi
2018	C	`conf`	Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network. ISCAS Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi, Kazuki Maeda, Ken Takeuchi
2018	—	`conf`	Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs. VLSI-DAT Yutaka Adachi, Chihiro Matsui, Ken Takeuchi
2018	—	`conf`	Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x. ESSDERC Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Ken Takeuchi
2018	—	`conf`	Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs. IRPS Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi
2018	—	`conf`	Improvement of Endurance and Data-retention in 40nm TaOX-based ReRAM by Finalize Verify. NVMTS Shouhei Fukuyama, Shinpei Matsuda, Ryutaro Yasuhara, Ken Takeuchi
2018	C	`conf`	Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition. ISCAS Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
2018	—	`conf`	Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM. NVMTS Reika Kinoshita, Chihiro Matsui, Shinpei Matsuda, Yutaka Adachi, Ken Takeuchi
2018	—	`conf`	New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai
2018	—	`conf`	Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAM. ESSDERC Kazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara
2018	—	`conf`	Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature. NVMTS Atsuya Suzuki, Chihiro Matsui, Ken Takeuchi
2018	J	`jnl`	Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test. IEICE Trans. Electron. Yusuke Yamaga, Chihiro Matsui, Yukiya Sakaki, Ken Takeuchi
2018	—	`conf`	Suppression of endurance-stressed data-retention failures of 40nm TaOx-based ReRAM. IRPS Shouhei Fukuyama, Kazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara
2018	J	`jnl`	Write and Read Frequency-Based Word-Line Batch V IEEE J. Solid State Circuits Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi
2017	—	`conf`	0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives. ISQED Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi
2017	—	`conf`	12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. CICC Yoshiaki Deguchi, Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi
2017	—	`conf`	22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash. ESSDERC Chihiro Matsui, Ken Takeuchi
2017	J	`jnl`	Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory. Proc. IEEE Chihiro Matsui, Chao Sun, Ken Takeuchi
2017	J	`jnl`	Image Retrieval Method for Multiscale Objects from Optical Colonoscopy Images. Int. J. Biomed. Imaging Hirokazu Nosato, Hidenori Sakanashi, Eiichi Takahashi, Masahiro Murakawa, Hiroshi Aoki, Ken Takeuchi, Yasuo Suzuki
2017	—	`conf`	MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage. A-SSCC Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi
2017	—	`conf`	Study of error repeatability and recovery in 40nm TaOx ReRAM. ESSDERC Takashi Inose, Seiichi Aritome, Ryutaro Yasuhara, Satoshi Mishima, Ken Takeuchi
2017	—	`conf`	Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data. A-SSCC Yoshiaki Deguchi, Ken Takeuchi
2017	J	`jnl`	Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs. IEICE Trans. Electron. Tomoaki Yamada, Chihiro Matsui, Ken Takeuchi
2017	J	`jnl`	Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD. IEEE Trans. Very Large Scale Integr. Syst. Chihiro Matsui, Asuka Arakawa, Chao Sun, Ken Takeuchi
2016	J	`jnl`	Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications. IEEE J. Solid State Circuits Tomoya Ishii, Sheyang Ning, Masahiro Tanaka, Kota Tsurumi, Ken Takeuchi
2016	J	`jnl`	An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
2016	J	`jnl`	Design guidelines of storage class memory/flash hybrid solid-state drive considering system architecture, algorithm and workload characteristic. IEEE Trans. Consumer Electron. Chao Sun, Shun Okamoto, Shogo Hachiya, Tomoaki Yamada, Ken Takeuchi
2016	—	`conf`	Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process. ESSCIRC Masahiro Tanaka, Kota Tsurumi, Tomoya Ishii, Ken Takeuchi
2016	J	`jnl`	LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives. IEEE Trans. Very Large Scale Integr. Syst. Chao Sun, Ayumi Soga, Chihiro Matsui, Asuka Arakawa, Ken Takeuchi
2016	J	`jnl`	Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. IEEE J. Solid State Circuits Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi
2016	—	`ch.`	System-Level Considerations on Design of 3D NAND Flash Memories. 3D Flash Memories Chao Sun, Ken Takeuchi
2016	J	`jnl`	Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. IEEE Trans. Very Large Scale Integr. Syst. Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi
2016	J	`jnl`	Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths. IEICE Trans. Electron. Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning, Ken Takeuchi
2016	—	`conf`	Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers. VLSI Circuits Atsuro Kobayashi, Tsukasa Tokutomi, Ken Takeuchi
2015	—	`conf`	0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications. A-SSCC Tomoya Ishii, Shogo Hachiya, Sheyang Ning, Masahiro Tanaka, Ken Takeuchi
2015	—	`conf`	7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. ISSCC Tsukasa Tokutomi, Masafumi Doi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Ken Takeuchi
2015	J	`jnl`	A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. IEICE Trans. Electron. Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
2015	—	`conf`	Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory. 3DIC Shogo Hachiya, Takahiro Onagi, Sheyang Ning, Ken Takeuchi
2015	J	`jnl`	Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. IEEE Trans. Circuits Syst. I Regul. Pap. Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi
2015	J	`jnl`	Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). IEEE Trans. Circuits Syst. I Regul. Pap. Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi
2015	—	`conf`	Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
2015	—	`conf`	Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten. VLSIC Shuhei Tanakamaru, Hiroki Yamazawa, Ken Takeuchi
2015	—	`conf`	Reliability enhancement of 1Xnm TLC for cold flash and millennium memories. VLSIC Senju Yamazaki, Shuhei Tanakamaru, Sakuya Suzuki, Tomoko Ogura Iwasaki, Shogo Hachiya, Ken Takeuchi
2015	J	`jnl`	SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform. IEEE Trans. Circuits Syst. I Regul. Pap. Chao Sun, Asuka Arakawa, Ken Takeuchi
2014	—	`conf`	19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. ISSCC Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi
2014	J	`jnl`	A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD. IEEE Trans. Circuits Syst. I Regul. Pap. Chao Sun, Kousuke Miyaji, Koh Johguchi, Ken Takeuchi
2014	J	`jnl`	A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories. IEICE Trans. Electron. Koh Johguchi, Toru Egami, Kousuke Miyaji, Ken Takeuchi
2014	—	`conf`	A workload-aware-design of 3D-NAND flash memory for enterprise SSDs. ISQED Chao Sun, Ayumi Soga, Takahiro Onagi, Koh Johguchi, Ken Takeuchi
2014	—	`conf`	Application-aware solid-state drives (SSDs) with adaptive coding. VLSIC Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi
2014	J	`jnl`	Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD. IEEE Trans. Circuits Syst. I Regul. Pap. Chao Sun, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi, Ken Takeuchi
2014	C	`conf`	Hybrid solid-state storage system with storage class memory and NAND flash memory for big-data application. ISCAS Ken Takeuchi
2014	J	`jnl`	NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
2014	J	`jnl`	NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance. IEICE Trans. Electron. Koh Johguchi, Kasuaki Yoshioka, Ken Takeuchi
2013	J	`jnl`	A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. IEEE J. Solid State Circuits Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi
2013	J	`jnl`	Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). IEEE J. Solid State Circuits Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
2013	—	`conf`	Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. ASP-DAC Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
2013	—	`conf`	Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression. ASP-DAC Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi
2013	—	`conf`	Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory. CICC Ken Takeuchi
2013	—	`conf`	Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. ISSCC Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
2012	—	`conf`	A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. ISSCC Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi
2012	J	`jnl`	Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor. IEICE Trans. Electron. Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi
2012	J	`jnl`	Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. IEEE J. Solid State Circuits Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi
2012	J	`jnl`	Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs). IEICE Electron. Express Ken Takeuchi, Teruyoshi Hatanaka, Shuhei Tanakamaru
2012	J	`jnl`	Initialize and Weak-Program Erasing Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive. IEICE Trans. Electron. Kousuke Miyaji, Ryoji Yajima, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi
2012	J	`jnl`	Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu
2012	J	`jnl`	NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD. IEEE J. Solid State Circuits Teruyoshi Hatanaka, Ken Takeuchi
2012	J	`jnl`	Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi
2012	—	`conf`	Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. ISSCC Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
2012	—	`conf`	Robust VLSI circuit design & systems for sustainable society. ISSCC Ken Takeuchi, Jan Crols, Kevin Zhang, Mike Clinton, Tadaaki Yamauchi
2012	—	`conf`	x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression. VLSIC Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Chao Sun, Ken Takeuchi
2011	J	`jnl`	1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. IEEE J. Solid State Circuits Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2011	—	`conf`	95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. ISSCC Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, Ken Takeuchi
2011	J	`jnl`	A 0.5 V Operation V IEEE J. Solid State Circuits Shuhei Tanakamaru, Ken Takeuchi
2011	—	`conf`	A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives. 3DIC Teruyoshi Hatanaka, Koh Johguchi, Ken Takeuchi
2011	A	`conf`	Green high performance storage class memory & NAND flash memory hybrid SSD system. ISLPED Ken Takeuchi
2011	J	`jnl`	Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell IEICE Trans. Electron. Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi
2011	J	`jnl`	Improvement of Read Margin and Its Distribution by V IEEE J. Solid State Circuits Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi
2011	—	`conf`	Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM. CICC Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi
2011	—	`conf`	Ultra-low voltage VLSIs for energy efficient systems. ISSCC Ken Takeuchi, Ken Chang, Kevin Zhang, Tadaaki Yamauchi, Roberto Gastaldi
2010	—	`conf`	Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. CICC Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi
2010	J	`jnl`	Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives. IEEE J. Solid State Circuits Teruyoshi Hatanaka, Ryoji Yajima, Takeshi Horiuchi, Shouyu Wang, Xizhen Zhang, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi
2010	J	`jnl`	Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. IEICE Trans. Electron. Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2010	—	`conf`	Silicon 3D-integration technology and systems. ISSCC Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai
2009	—	`conf`	A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. ISSCC Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2009	—	`conf`	Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. 3DIC Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2009	A	`conf`	Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. ISLPED Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2009	J	`jnl`	Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD). IEEE J. Solid State Circuits Ken Takeuchi
2009	—	`conf`	SSD memory subsystem innovation. ISSCC Ken Takeuchi
2007	J	`jnl`	A 56-nm CMOS 99-mm IEEE J. Solid State Circuits Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima
2006	—	`conf`	A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput. ISSCC Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima
2002	J	`jnl`	A 125-mm IEEE J. Solid State Circuits Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che
2002	J	`jnl`	Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid State Circuits Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura
2001	J	`jnl`	A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories. IEEE J. Solid State Circuits Ken Takeuchi, Tomoharu Tanaka
2000	J	`jnl`	A source-line programming scheme for low-voltage operation NAND flash memories. IEEE J. Solid State Circuits Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui
1999	J	`jnl`	A 130-mm/ IEEE J. Solid State Circuits Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui
1999	J	`jnl`	A negative V IEEE J. Solid State Circuits Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui
1998	J	`jnl`	A multipage cell architecture for high-speed programming multilevel NAND flash memories. IEEE J. Solid State Circuits Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa
1997	J	`jnl`	A compact on-chip ECC for low cost flash memories. IEEE J. Solid State Circuits Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi
1996	J	`jnl`	A double-level-V IEEE J. Solid State Circuits Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura
1983	—	`conf`	Design Considerations for an Information Query Computer. Advanced Database Machine Architecture Akira Sekino, Ken Takeuchi, Takenori Makino, Katsuya Hakozaki, Tsugunori Doi, Tatsuo Goto
1983	J	`jnl`	Relational Data Base Systems INQ and RIOS. IEEE Database Eng. Bull. Kazuyuki Hara, Tatsuo Gotoh, Tsuyoshi Miyazaki, Ken Takeuchi, Shigeru Mabuchi