Ken Mai - RankMe

75 papers A* 7A 18B 1C 6Misc 1Journal 12Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A 748 GOPS/W RISC-V SoC with Reconfigurable Custom Instructions via a Synthesized eFPGA with 1.8µs Configuration Time in 22nm FinFET. CICC Prashanth Mohan, Siddharth Das, Ken Mai
2025	J	`jnl`	A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET. IEEE Solid State Circuits Lett. Prashanth Mohan, Siddharth Das, Ken Mai
2025	A	`conf`	A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process. DATE Prashanth Mohan, Siddharth Das, Oguz Atli, Josh Joffrion, Ken Mai
2025	—	`conf`	Towards an Algorithm-based Approach for Soft Error Tolerance using Interval Arithmetic. HPEC Larry Tang, Varun Kumar, Matthew Ngaw, Siddharth Singh, Devdutt Nadkarni, Lohith Tummala, Ken Mai, Franz Franchetti
2024	—	`conf`	A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm. HCS Larry Tang, Siyuan Chen, Keshav Harisrikanth, Guanglin Xu, Franz Franchetti, Ken Mai
2023	—	`conf`	A 10.33 μJ/encryption Homomorphic Encryption Engine in 28nm CMOS with 4096-degree 109-bit Polynomials for Resource-Constrained IoT Clients. ESSCIRC Siddharth Das, McKenzie van der Hagen, Swarali Patil, Cagri Erbagci, Brandon Lucia, Ken Mai
2023	C	`conf`	MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS. ISCAS Graham Gobieski, Oguz Atli, Cagri Erbagci, Ken Mai, Nathan Beckmann, Brandon Lucia
2022	—	`conf`	A High Throughput Hardware Accelerator for FFTW Codelets: A First Look. HPEC Larry T. Pileggi, Siyuan Chen, Keshav Harisrikanth, Guanglin Xu, Ken Mai, Franz Franchetti
2022	J	`jnl`	Logic Locking - Connecting Theory and Practice. IACR Cryptol. ePrint Arch. Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence T. Pileggi, Vipul Goyal, Bryan Parno
2022	A	`conf`	Towards Specialized Hardware for Learning-based Visual Odometry on the Edge. IROS Siyuan Chen, Ken Mai
2021	A	`conf`	Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. DATE Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai
2021	J	`jnl`	Split-Chip Design to Prevent IP Reverse Engineering. IEEE Des. Test Samuel Pagliarini, Joseph Sweeney, Ken Mai, R. D. Shawn Blanton, Larry T. Pileggi, Subhasish Mitra
2021	A	`conf`	Top-down Physical Design of Soft Embedded FPGA Fabrics. FPGA Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai
2020	A	`conf`	A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. FPGA Prashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai
2020	C	`conf`	ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS. ICCD Prashanth Mohan, Wen Wang, Bernhard Jungk, Ruben Niederhagen, Jakub Szefer, Ken Mai
2019	—	`conf`	An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS. ESSCIRC Burak Erbagci, Nail Etkin Can Akkaya, Cagri Erbagci, Ken Mai
2019	J	`jnl`	Secure hardware-entangled field programmable gate arrays. J. Parallel Distributed Comput. Burak Erbagci, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, Ken Mai
2018	—	`conf`	A compact energy-efficient pseudo-static camouflaged logic family. HOST Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai
2018	—	`conf`	A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD. ISSCC Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai
2018	J	`jnl`	Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming. CoRR Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch
2018	J	`jnl`	Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory. CoRR Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Saugata Ghose, Onur Mutlu
2018	J	`jnl`	Read Disturb Errors in MLC NAND Flash Memory. CoRR Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, Onur Mutlu
2018	—	`conf`	Secure chip odometers using intentional controlled aging. HOST Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai
2017	A*	`conf`	Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. HPCA Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch
2016	—	`conf`	A secure camouflaged threshold voltage defined logic family. HOST Burak Erbagci, Cagri Erbagci, Nail Etkin Can Akkaya, Ken Mai
2016	—	`conf`	Scalable High-Radix Modular Crossbar Switches. Hot Interconnects Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai
2015	—	`conf`	A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm. CICC Burak Erbagci, Nail Etkin Can Akkaya, Craig Teegarden, Ken Mai
2015	—	`conf`	A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. A-SSCC Burak Erbagci, Fangfei Liu, Cagla Cakir, Nail Etkin Can Akkaya, Ruby B. Lee, Ken Mai
2015	—	`conf`	A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. HOST Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai
2015	J	`jnl`	A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. IACR Cryptol. ePrint Arch. Mudit Bhargava, Ken Mai
2015	—	`conf`	Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks. ISQED Yu Cai, Ken Mai, Onur Mutlu
2015	B	`conf`	DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. ISPASS Michael Papamichael, Cagla Cakir, Chen Sun, Chia-Hsin Owen Chen, James C. Hoe, Ken Mai, Li-Shiuan Peh, Vladimir Stojanovic
2015	A*	`conf`	Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. HPCA Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu
2015	—	`conf`	Deeply hardware-entangled reconfigurable logic and interconnect. ReConFig Burak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai
2015	J	`jnl`	Guest Editorial Special Section on Hardware Security and Trust. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad-Reza Sadeghi, Swarup Bhunia
2015	A	`conf`	High-efficiency crossbar switches using capacitively coupled signaling. ISLPED Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai
2015	—	`conf`	Modeling and Design of High-Radix On-Chip Crossbar Switches. NOCS Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai
2015	—	`conf`	Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. HOST Mudit Bhargava, Kaship Sheikh, Ken Mai
2015	A	`conf`	Statistical Learning in Chip (SLIC). ICCAD Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2014	A	`conf`	An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. DATE Mudit Bhargava, Ken Mai
2014	A*	`conf`	Neighbor-cell assisted error correction for MLC NAND flash memories. SIGMETRICS Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman S. Unsal, Adrián Cristal, Ken Mai
2014	—	`conf`	SLIC: Statistical learning in chip. ISIC Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2013	A	`conf`	A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. CHES Mudit Bhargava, Ken Mai
2013	C	`conf`	Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. PRDC Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai, Babak Falsafi
2013	C	`conf`	Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. ICCD Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai
2013	A	`conf`	SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. ITC Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai
2013	A	`conf`	Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. DATE Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai
2012	—	`conf`	6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. CICC Cagla Cakir, Mudit Bhargava, Ken Mai
2012	—	`conf`	Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. CICC Mudit Bhargava, Cagla Cakir, Ken Mai
2012	A	`conf`	Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. DATE Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai
2012	C	`conf`	Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. ICCD Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal, Osman S. Ünsal, Ken Mai
2012	A	`conf`	Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. FPGA Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai
2012	—	`conf`	Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. HOST Mudit Bhargava, Cagla Cakir, Ken Mai
2011	A	`conf`	CoRAM: an in-fabric memory architecture for FPGA-based computing. FPGA Eric S. Chung, James C. Hoe, Ken Mai
2011	Misc	`conf`	FPGA-Based Solid-State Drive Prototyping Platform. FCCM Yu Cai, Erich F. Haratsch, Mark P. McCartney, Ken Mai
2011	A	`conf`	FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai
2010	—	`conf`	A Comparison of Power-analysis-resistant Digital Circuits. HOST Eric Menendez, Ken Mai
2010	—	`conf`	Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. HOST Mudit Bhargava, Cagla Cakir, Ken Mai
2010	—	`ed.`	HOST 2010, Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 13-14 June 2010, Anaheim Convention Center, California, USA HOST Jim Plusquellic, Ken Mai
2010	—	`conf`	Side-channel Attack Resistant ROM-based AES S-Box. HOST Craig Teegarden, Mudit Bhargava, Ken Mai
2010	A*	`conf`	Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? MICRO Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai
2010	A*	`conf`	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. DAC Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun
2009	C	`conf`	A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. ICCD Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun
2009	—	`conf`	Low-overhead, digital offset compensated, SRAM sense amplifiers. CICC Mudit Bhargava, Mark P. McCartney, Alexander Hoefler, Ken Mai
2009	J	`jnl`	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi
2008	—	`conf`	A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style. HOST Eric Menendez, Ken Mai
2008	A	`conf`	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2008	J	`jnl`	Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard
2008	—	`conf`	Mismatch analysis and statistical design at 65 nm and below. CICC Larry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai, Jonathan E. Proesel
2008	—	`conf`	Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi
2007	A*	`conf`	Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. MICRO Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe
2007	A	`conf`	PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2005	J	`jnl`	Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. IEEE J. Solid State Circuits Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz
2000	A*	`conf`	Smart Memories: a modular reconfigurable architecture. ISCA Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
1999	A	`conf`	Interconnect scaling implications for CAD. ICCAD Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz