Keji Zhou

24 papers C 4Journal 17Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 21-Transistor Single-Phase-Clocked Flip-Flop With Low Leakage Current for Near-Threshold Voltage Operation.
IEEE Trans. Circuits Syst. II Express Briefs
Chenyang Li, Jingsong Zhang, Jin Xin, Keji Zhou, Jinhao Liang, Siyuan Ouyang, Fangduo Zhu, Xumeng Zhang, Qi Liu
2025 C conf
A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit.
ISCAS
Honghu Yang, Yongkang Han, Tianci Cai, Chengshuo Yu, Keji Zhou, Jianguo Yang
2025 C conf
A High-Density RRAM-Based Ising Machine with Analog In-Memory Operation for Solving Combinatorial Optimization Problems.
ISCAS
Jingxin Deng, Keji Zhou, Honghu Yang, Chengshuo Yu, Jianguo Yang
2025 J jnl
A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons With (Anti-) Integration Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Qiqiao Wu, Honghu Yang, Yixuan Liu, Yue Cao, Yongkang Han, Haijun Jiang, Keji Zhou, Hailan Yi, Jianguo Yang, Qi Liu
2025 C conf
A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme.
ISCAS
Yue Cao, Yuanyuan Han, Keji Zhou, Chengshuo Yu, Tianci Cai, Jianguo Yang
2025 J jnl
Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yixuan Liu, Qiqiao Wu, Honghu Yang, Chengshuo Yu, Keji Zhou, Yu Jiang, Haijun Jiang, Hailan Yi, Xiaoyong Xue, Jianguo Yang, Xiaoyang Zeng
2025 C conf
SRIF: Energy- and Area-Efficient Soft Reset Integrate-and-Fire Neuron for High-Accuracy Spiking Neural Network.
ISCAS
Tianci Cai, Qiqiao Wu, Yixuan Liu, Yue Cao, Yu Jiang, Keji Zhou, Jianguo Yang
2024 J jnl
A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips.
IEEE Trans. Circuits Syst. II Express Briefs
Siyuan Ouyang, Keji Zhou, Hao Jiang, Chenyang Li, Jinhao Liang, Fangduo Zhu, Xumeng Zhang, Qi Liu
2024 J jnl
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer.
IEEE Trans. Very Large Scale Integr. Syst.
Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen
2023 J jnl
A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng
2023 J jnl
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs
Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu, Xiaoyang Zeng
2023 J jnl
Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hao Jiang, Jikai Lu, Chenggao Zhang, Shuangzhu Tang, Junjie An, Lingli Cheng, Jian Lu, Jinsong Wei, Keji Zhou, Xumeng Zhang, Tuo Shi, Qi Liu
2023 J jnl
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jingwen Jiang, Keji Zhou, Jinhao Liang, Fengshi Tian, Chenyang Zhao, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng
2022 — conf
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits.
AICAS
Chen Mu, Yunzhengmao Wang, Jiapei Zheng, Shiwei Liu, Keji Zhou, Shan Tang, Chixiao Chen, Qi Liu
2022 J jnl
A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices.
Microelectron. J.
Jianguo Yang, Ruijun Lin, Keji Zhou, Yuejun Zhang, Xiaoyong Xue, Hangbing Lv
2022 J jnl
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu
2022 J jnl
A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications.
Microelectron. J.
Keji Zhou, Ruijun Lin, Zhiwang Guo, Yixuan Liu, Jingwen Jiang, Chenyang Zhao, Jinbei Fang, Xiaoxin Xu, Xiaoyong Xue, Xiaoyang Zeng
2022 J jnl
Toward Practical Temporal Diversity Coherent Combining Based Variable Data-Rate Free Space Optical Communication Systems.
IEEE Access
Faming Li, Sheng Cui, Yanan Chen, Chenjie Rao, Yicong Tu, Keji Zhou, Deming Liu
2021 J jnl
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng
2021 J jnl
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications.
IEEE J. Solid State Circuits
Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Ming-e Jing, Jing Li, Xiaoyang Zeng, Ming Liu
2020 J jnl
Toward Practical Digital Phase Alignment for Coherent Beam Combining in Multi-Aperture Free Space Coherent Optical Receivers.
IEEE Access
Chenjie Rao, Sheng Cui, Yicong Tu, Keji Zhou, Deming Liu
2019 — conf
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications.
ASICON
Yujie Cai, Keji Zhou, Xiaoyong Xue, Mingyu Wang, Xiaoyang Zeng
2018 — conf
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F
A-SSCC
Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Mingyu Wang, Ming-e Jing, Wenjun Liu, Xiaoyang Zeng, Steve S. Chung, Jing Li, Ming Liu
2016 J jnl
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng