Keizo Hiraga

13 papers Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
Application of Nonvolatile IP with MTJ to eFPGA.
NVMSA
Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2025 J jnl
Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP.
IPSJ Trans. Syst. LSI Des. Methodol.
Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2025 — conf
Proposal for Non-Volatilization of eFPGA Core.
COOL CHIPS
Keizo Hiraga, Kenshu Seto, Kazuhiro Bessho, Masahiro Iida
2024 J jnl
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations.
IEEE Trans. Very Large Scale Integr. Syst.
Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho
2023 — conf
A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing.
VLSI Technology and Circuits
Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi
2023 — conf
A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package.
candar
Shota Nakabeppu, Nobuyuki Yamasaki, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho
2023 J jnl
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
2021 — conf
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops.
MCSoC
Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
2020 — conf
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization.
COOL CHIPS
Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda
2018 — conf
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops.
ReConFig
Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
2018 — conf
Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application.
NVMSA
Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami
2015 — conf
Impact of fin shape variability on device performance towards 10nm node.
ICICDT
Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean
2000 J jnl
A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming.
IEEE J. Solid State Circuits
Hiromi Nobukata, Shunsuke Takagi, Keizo Hiraga, Takeshi Ohgishi, Masaru Miyashita, Kazuto Kamimura, Shinji Hiramatsu, Kiyohisa Sakai, Takahiro Ishida, Hideki Arakawa, Masahiko Itoh, Ihachi Naiki, Masanori Noda