Keith A. Bowman

70 papers A* 3A 11Journal 22Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction. ISSCC Yimai Peng, Daniel Yingling, Basma Hajri, Robert Vachon, Fikre Tsigabu Gebreyohannes, Vincent Li, Ghanshyam Chhetri, Keith A. Bowman
2026	J	`jnl`	An Adaptive Clock Duty-Cycle Controller to Mitigate Aging-Induced Clock Duty-Cycle Distortion in Automotive and IoT Processors. IEEE J. Solid State Circuits Daniel Yingling, Yimai Peng, Robert Vachon, Dipti Pal, Sagar Jariwala, Felipe G. Cabral, Shih-Hsin Hu, Rajan Verma, Vamshidhar Chiranji, Anil Kumar, Santanu Sarma, Keith A. Bowman
2024	—	`conf`	14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion. ISSCC Daniel Yingling, Yimai Peng, Robert Vachon, Dipti Pal, Sagar Jariwala, Felipe G. Cabral, Jason Hu, Rajan Verma, Vamshidhar Chiranji, Anil Kumar, Santanu Sarma, Keith A. Bowman
2022	—	`conf`	Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators. CICC Zhaoqing Wang, Sung Justin Kim, Keith A. Bowman, Mingoo Seok
2021	—	`conf`	35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon™ Processor. ISSCC Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Suresh Venkumahanti
2021	J	`jnl`	A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor. IEEE J. Solid State Circuits Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2021	J	`jnl`	A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor. IEEE J. Solid State Circuits Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2021	—	`conf`	F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology. ISSCC Nick Van Helleputte, Arijit Raychowdhury, Ping-Hsuan Hsieh, Jun Deguchi, Matteo Perenzoni, Esther Rodríguez-Villegas, Long Yan, Andreia Cathelin, Keith A. Bowman, Chris Van Hoof
2021	—	`conf`	SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham
2021	—	`conf`	Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE. ISSCC Ping-Hsuan Hsieh, Mingoo Seok, Keith A. Bowman
2021	—	`conf`	Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee. ISSCC Arijit Raychowdhury, Mijung Noh, Keith A. Bowman
2020	—	`conf`	A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor. VLSI Circuits Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2020	—	`conf`	Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP. CICC Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2019	—	`conf`	A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. ISSCC Francois Atallah, Keith A. Bowman, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Yu Sun, Brad Appel, Anthony Polomik, Mahesh Harinath, Joshua Morelli, Thomas Moore, Nathaniel Reeves, Amer Cassier, Arijit Raychowdhury
2019	—	`conf`	A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. VLSI Circuits Keith A. Bowman, Samantak Gangopadhyay, Francois Atallah, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Anthony Polomik, Mahesh Harinath, Nathaniel Reeves, Amer Cassier, Brad Appel, Arijit Raychowdhury
2019	J	`jnl`	A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
2018	—	`conf`	A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. VLSI Circuits Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman
2018	—	`conf`	An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
2018	J	`jnl`	Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Keith A. Bowman, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak
2017	—	`conf`	Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. CICC Samantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury
2017	—	`conf`	F1: Integrated voltage regulators for SoC and emerging IoT systems. ISSCC Makoto Takamiya, Yogesh K. Ramadass, Keith A. Bowman, Gerard Villar Pique, Shuichi Nagai, Dennis Sylvester
2016	J	`jnl`	3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication. J. Signal Process. Syst. Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
2016	J	`jnl`	A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. IEEE J. Solid State Circuits Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine
2015	—	`conf`	8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. ISSCC Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine
2015	—	`conf`	A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. CICC Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine
2014	—	`conf`	3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. SiPS Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
2014	—	`conf`	5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
2014	—	`conf`	Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. CICC Alex Park, Venkat Narayanan, Keith A. Bowman, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine
2014	A	`conf`	Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. ITC Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine
2013	J	`jnl`	A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz
2013	J	`jnl`	Adaptive and Resilient Circuits for Dynamic Variation Tolerance. IEEE Des. Test Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De
2013	A	`conf`	Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz
2013	—	`conf`	Welcome to ISQED 2013. ISQED Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi
2012	—	`conf`	A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2012	—	`conf`	Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman
2012	—	`ed.`	Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012 ISQED Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni
2011	J	`jnl`	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
2011	J	`jnl`	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
2011	J	`jnl`	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2011	J	`jnl`	Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De
2011	J	`jnl`	Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar
2010	—	`conf`	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	—	`conf`	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
2010	—	`conf`	PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep P. Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
2010	—	`conf`	Resilient design in scaled CMOS for energy efficiency. ASP-DAC James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2010	A	`conf`	Resilient microprocessor design for high performance & energy efficiency. ISLPED Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	A	`conf`	Resilient microprocessor design for improving performance and energy efficiency. ICCAD Keith A. Bowman, James W. Tschanz
2010	—	`conf`	Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar
2009	A*	`conf`	Circuit techniques for dynamic variation tolerance. DAC Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar
2009	J	`jnl`	Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2009	J	`jnl`	Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors. IEEE Trans. Very Large Scale Integr. Syst. Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson
2009	A	`conf`	Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik
2008	—	`conf`	Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2007	A*	`conf`	Comparative Analysis of Conventional and Statistical Design Techniques. DAC Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De
2007	A	`conf`	Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. ISLPED Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson
2006	J	`jnl`	Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
2006	A	`conf`	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
2006	—	`conf`	Tutorial II: Variability and Its Impact on Design. ISQED Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
2005	A	`conf`	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De
2005	A	`conf`	Total power-optimal pipelining and parallel processing under process variations in nanometer technology. ICCAD Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
2005	A*	`conf`	Variation-tolerant circuits: circuit solutions and techniques. DAC James W. Tschanz, Keith A. Bowman, Vivek De
2002	J	`jnl`	Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits Keith A. Bowman, Steven G. Duvall, James D. Meindl
2001	—	`conf`	Impact of within-die parameter fluctuations on future maximum clock frequency distributions. CICC Keith A. Bowman, James D. Meindl
2001	J	`jnl`	Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
2000	J	`jnl`	A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
2000	—	`conf`	Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
2000	J	`jnl`	Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance. IEEE J. Solid State Circuits Keith A. Bowman, Xinghai Tang, John C. Eble, James D. Menldl
2000	A	`conf`	Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
1999	J	`jnl`	A physical alpha-power law MOSFET model. IEEE J. Solid State Circuits Keith A. Bowman, Blanca Austin, John C. Eble, Xinghai Tang, James D. Meindl