Keisuke Inoue - RankMe

46 papers A 1B 2C 5Misc 1Journal 12Unranked 24

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Establishing Utilization Decision Criteria for Open-Source Software Projects Based on Issue Resolution Time Evaluation. ICSTW Keisuke Inoue, Kazuhiko Tsuda
2024	—	`conf`	Study on Vibration Characteristics of Bolted and Bonded Joints by Using Acceleration Sensors. IEEE SENSORS Shogo Isobe, Tristan Samuel Britton Fujimori, Yoshinao Kishimoto, Yukiyoshi Kobayashi, Keisuke Inoue
2020	—	`conf`	Removing Reflection from In-vehicle Camera Image. VISIGRAPP (4: VISAPP) Keisuke Inoue, Fumihiko Sakaue, Jun Sato
2019	C	`conf`	An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures. VLSI-SoC Keisuke Inoue
2018	—	`conf`	Automatic Examination-Based Whitelist Generation for XSS Attack Detection. BWCCA Keisuke Inoue, Toshiki Honda, Kohei Mukaiyama, Tetsushi Ohki, Masakatsu Nishigaki
2017	—	`conf`	A dependable ASIC architecture with RT-level rollback for controller soft error recovery. NORCAS Keisuke Inoue
2016	—	`conf`	ECC module optimization for storage transient error-tolerant ASICs. ICECS Keisuke Inoue
2015	—	`conf`	Bitwidth-aware register allocation and binding for clock period minimization. MWSCAS Keisuke Inoue, Mineo Kaneko
2014	—	`conf`	An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
2014	Misc	`conf`	Spanning Distribution Forests of Graphs - (Extended Abstract). FAW Keisuke Inoue, Takao Nishizeki
2013	J	`jnl`	Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko
2013	J	`jnl`	Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko
2012	J	`jnl`	A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko
2012	—	`conf`	Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. ACM Great Lakes Symposium on VLSI Keisuke Inoue, Mineo Kaneko
2012	—	`conf`	Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. ASP-DAC Keisuke Inoue, Mineo Kaneko
2012	—	`conf`	Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis. ISQED Keisuke Inoue, Mineo Kaneko
2012	C	`conf`	Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis. ISCAS Keisuke Inoue, Mineo Kaneko
2012	—	`conf`	Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis. MWSCAS Keisuke Inoue, Mineo Kaneko
2011	J	`jnl`	Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2011	C	`conf`	Early planning for RT-level delay insertion during clock skew-aware register binding. VLSI-SoC Keisuke Inoue, Mineo Kaneko
2011	J	`jnl`	Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. Inf. Media Technol. Keisuke Inoue, Mineo Kaneko
2011	J	`jnl`	Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. IPSJ Trans. Syst. LSI Des. Methodol. Keisuke Inoue, Mineo Kaneko
2011	—	`conf`	Ordered coloring-based resource binding for datapaths with improved skew-adjustability. ACM Great Lakes Symposium on VLSI Mineo Kaneko, Keisuke Inoue
2011	C	`conf`	Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. ISCAS Keisuke Inoue, Mineo Kaneko
2010	—	`conf`	A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. ACM Great Lakes Symposium on VLSI Keisuke Inoue, Mineo Kaneko
2010	—	`conf`	Optimal register assignment with minimum-delay compensation for latch-based design. APCCAS Keisuke Inoue, Mineo Kaneko
2009	—	`conf`	Discourse analysis of online chat reference interviews for modeling online information-seeking dialogues. ASIST Keisuke Inoue
2009	J	`jnl`	Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2009	—	`conf`	Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008	—	`ed.`	ACL 2008, Proceedings of the 46th Annual Meeting of the Association for Computational Linguistics, June 15-20, 2008, Columbus, Ohio, USA, Student Research Workshop ACL (Student Research Workshop) Ebru Arisoy, Keisuke Inoue, Wolfgang Maier
2008	J	`jnl`	Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008	C	`conf`	Safe clocking register assignment in datapath synthesis. ICCD Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2006	—	`conf`	Social dynamics of free and open source team communications. OSS James Howison, Keisuke Inoue, Kevin Crowston
2005	A	`conf`	Knowledge Discovery from Heterogeneous Dynamic Systems using Change-Point Correlations. SDM Tsuyoshi Idé, Keisuke Inoue
2003	J	`jnl`	A Novel Robot Vision Applicable to Real-time Target Tracking. J. Robotics Mechatronics Kazuhiro Shimonomura, Keisuke Inoue, Seiji Kameda, Tetsuya Yagi
2001	J	`jnl`	A 250-MHz single-chip multiprocessor for audio and video signal processing. IEEE J. Solid State Circuits Tatsuya Koyama, Keisuke Inoue, Hirokazu Hanaki, Masahiro Yasue, Eiji Iwata
2001	J	`jnl`	Face clustering of a large-scale CAD model for surface mesh generation. Comput. Aided Des. Keisuke Inoue, Takayuki Itoh, Atsushi Yamada, Tomotake Furuhata, Kenji Shimada
2000	—	`conf`	An Approach for Generating Meshes Similar to A Reference Mesh. IMR Atsushi Yamada, Keisuke Inoue, Takayuki Itoh, Kenji Shimada
1999	—	`conf`	Clustering Large Number of Faces for 2-Dimensional Mesh Generation. IMR Keisuke Inoue, Takayuki Itoh, Atsushi Yamada, Tomotake Furuhata, Kenji Shimada
1999	—	`conf`	ISIS: Multiprocessor Simulator Library. Applied Informatics Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano
1998	—	`conf`	Automated Conversion of 2D Triangular Mesh into Quadrilateral Mesh with Directionality Control. IMR Takayuki Itoh, Kenji Shimada, Keisuke Inoue, Atsushi Yamada, Tomotake Furuhata
1997	J	`jnl`	A study on snoop cache systems for single-chip multiprocessors. Syst. Comput. Jpn. Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano
1997	—	`conf`	Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. Euro-Par Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano
1997	—	`conf`	Traffic Control Model with Neural Network Analogy. ICONIP (2) Toru Ohira, Keisuke Inoue, Yoshiteru Takeshima
1996	B	`conf`	ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. FPL Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano
1991	B	`conf`	An ATMS-based geometric constraint solver for 3D CAD. ICTAI Shuichi Shimizu, Keisuke Inoue, Masayuki Numao