| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2018 | Misc | conf |
CISIS
|
| 2017 | — | conf |
ECOC
|
| 2015 | — | conf |
ECOC
|
| 2015 | J | jnl |
IEICE Trans. Inf. Syst.
|
| 2014 | J | jnl |
SIGARCH Comput. Archit. News
|
| 2014 | B | conf |
FPL
|
| 2014 | — | conf |
ARC
|
| 2013 | — | conf |
CANDAR
|
| 2013 | J | jnl |
IEICE Trans. Inf. Syst.
|
| 2013 | — | conf |
Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator.
ReConFig
|
| 2012 | B | conf |
FPL
|
| 2012 | J | jnl |
IEICE Trans. Inf. Syst.
|
| 2012 | J | jnl |
SIGARCH Comput. Archit. News
|
| 2011 | J | jnl |
SIGARCH Comput. Archit. News
|
| 2011 | — | conf |
FPT
|
| 2011 | J | jnl |
SIGARCH Comput. Archit. News
|
| 2011 | B | conf |
FPL
|
| 2010 | — | conf |
ASAP
|
| 2010 | J | jnl |
SIGARCH Comput. Archit. News
|