Keishi Sakanushi

39 papers A 5C 3Misc 2Journal 13Unranked 16
YearRankTypeTitle / Venue / Authors
2013 J jnl
Electronic triage system for continuously monitoring casualties at disaster scenes.
J. Ambient Intell. Humaniz. Comput.
Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka
2012 J jnl
A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring.
IEICE Trans. Electron.
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2012 — conf
On-chip Communication Buffer Architecture Optimization Considering Bus Width.
MCSoC
Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2012 — conf
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion.
MCSoC
Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2011 — conf
Automated architecture exploration for low energy reconfigurable AGU.
ISOCC
Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2011 — conf
Biological information sensing technologies for medical, health care, and wellness applications.
ASP-DAC
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato
2011 — conf
Electronic Triage System: Casualties Monitoring System in the Disaster Scene.
3PGCIC
Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka
2011 J jnl
Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010 J jnl
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions.
Inf. Media Technol.
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010 J jnl
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions.
IPSJ Trans. Syst. LSI Des. Methodol.
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010 J jnl
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).
Inf. Media Technol.
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
2010 J jnl
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).
IPSJ Trans. Syst. LSI Des. Methodol.
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura
2010 C conf
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.
ISCAS
Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2010 — conf
Two-stage configurable decoder model for multiple forward error correction standards.
ESTIMedia
Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2009 J jnl
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2009 J jnl
Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moniem Wahdan, Masaharu Imai
2009 — conf
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
ASP-DAC
Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2007 — conf
A Block-Floating-Point Processor for Rapid Application Development.
ICASSP (2)
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi
2007 — conf
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.
ASP-DAC
Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2007 Misc conf
A low power VLIW processor generation method by means of extracting non-redundant activation conditions.
CODES+ISSS
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2007 J jnl
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto
2007 J jnl
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
CoRR
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2006 — conf
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.
VLSI-SoC (Selected Papers)
Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai
2006 Misc conf
Pack instruction generation for media pUsing multi-valued decision diagram.
CODES+ISSS
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa
2006 C conf
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.
VLSI-SoC
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2005 — conf
Enabling RTOS simulation modeling in a system level design language.
ASP-DAC
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2005 A conf
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC.
DATE
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2004 A conf
Architecture-Level Performance Estimation for IP-Based Embedded Systems.
DATE
Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2004 — conf
S-sequence: a new floorplan representation method preserving room abutment relationships.
ISCAS (4)
Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai
2004 — conf
Synthesizable HDL generation method for configurable VLIW processors.
ASP-DAC
Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2004 — conf
Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation.
ICDCS Workshops
H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
2003 C conf
A Code Selection Method for SIMD Processors with PACK Instructions.
SCOPES
Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai
2003 J jnl
An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuya Wakata, Hiroaki Saito, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata, Chikaaki Kodama
2003 — conf
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost.
ASP-DAC
Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani
2002 A conf
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.
DATE
Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin
2002 — conf
An improved method of convex-shaped block packing based on sequence-pair [VLSI layout].
APCCAS (2)
Hiroaki Saito, Kazuya Wakata, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata
2002 J jnl
Recognition of Floorplan by Parametric BSG for Reuse of Layout Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keishi Sakanushi, Zhonglin Wu, Yoji Kajitani
1998 A conf
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.
ICCAD
Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita
1998 A conf
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.
ICCAD
Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani