Keiko Abe - RankMe

15 papers A 2C 2Misc 1Journal 1Unranked 9

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2016	—	`conf`	7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
2015	—	`conf`	7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
2014	—	`conf`	Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2014	—	`conf`	Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". ASP-DAC Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
2014	Misc	`conf`	Pictogram-based tablet application enabling patient input of emotions and behaviors. AMIA Teruyoshi Hishiki, Hiroki Yasui, Yoshiko Matsunaga, Megumi Itoshima, Keiko Abe, Takahiko Norose, Takuro Tamura
2013	A	`conf`	D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2012	—	`conf`	Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita
2010	A	`conf`	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
2010	C	`conf`	Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. ISCAS Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima
2009	C	`conf`	Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
2007	J	`jnl`	3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
2006	—	`conf`	3D on-chip networking technology based on post-silicon devices for future networks-on-chip. Nano-Net Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
2006	—	`conf`	Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon
2005	—	`conf`	Physical random number generators for cryptographic application in mobile devices. ESSCIRC Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita