Keikichi Tamaru

31 papers A* 2A 5C 3Misc 3Journal 7Unranked 11

Year	Rank	Type	Title / Venue / Authors
2000	—	`conf`	A method for linking process-level variability to system performances. ASP-DAC Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru
1999	A*	`conf`	A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
1998	J	`jnl`	A memory efficient array architecture for real-time motion estimation. Syst. Comput. Jpn. Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru
1998	Misc	`conf`	A new architecture for in-memory image convolution. ICASSP Vasily G. Moshnyaga, Kazuhiro Suzuki, Keikichi Tamaru
1998	A	`conf`	A power optimization method considering glitch reduction by gate sizing. ISLPED Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
1998	J	`jnl`	Model-adaptable MOSFET parameter-extraction method using an intermediate model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
1998	A	`conf`	Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru
1998	Misc	`conf`	Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. ICASSP Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru
1997	—	`conf`	A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS Vasily G. Moshnyaga, Keikichi Tamaru
1997	—	`conf`	A current mode cyclic A/D converter with a 0.8 μm CMOS process. ASP-DAC Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
1997	—	`conf`	A functional memory type parallel processor for vector quantization. ASP-DAC Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru
1997	Misc	`conf`	A memory efficient array architecture for full-search block matching algorithm. ICASSP Vasily G. Moshnyaga, Keikichi Tamaru
1996	—	`conf`	Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
1995	C	`conf`	A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS Vasily G. Moshnyaga, Keikichi Tamaru
1995	C	`conf`	A New Algorithm for Sorting Problem with Reformed CAM. ISCAS Kuei-Ming Lu, Keikichi Tamaru
1995	—	`conf`	A model-adaptable MOSFET parameter extraction system. ASP-DAC Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru
1995	—	`conf`	A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru
1995	A	`conf`	An iterative gate sizing approach with accurate delay evaluation. ICCAD Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru
1995	J	`jnl`	High speed merged array multiplication. J. VLSI Signal Process. Farhad Fuad Islam, Keikichi Tamaru
1995	J	`jnl`	Register-Transfer Module Selection for Sub-Micron ASIC Design. IEICE Trans. Inf. Syst. Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru
1994	—	`conf`	Processing nested loop structure with data-flow dependence on a CAM-based processor HAPP. ISPAN Kuei-Ming Lu, Keikichi Tamaru
1993	C	`conf`	An Architecture for Intermediate Area-time Complexity Multiplier. ISCAS Farhad Fuad Islam, Keikichi Tamaru
1993	—	`conf`	High speed merged multiplication. ICASSP (1) Farhad Fuad Islam, Keikichi Tamaru
1993	A	`conf`	Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
1992	—	`conf`	Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
1991	A*	`conf`	Branch-and-Bound Placement for Building Block Layout. DAC Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru
1990	A	`conf`	Extraction of Functional Information from Combinatorial Circuits. ICCAD M. Ohmura, Hiroto Yasuura, Keikichi Tamaru
1990	J	`jnl`	Operational-amplifier compilation with performance optimization. IEEE J. Solid State Circuits Hidetoshi Onodera, Hiroyuki Kanbara, Keikichi Tamaru
1988	J	`jnl`	A cyclic A/D converter that does not require ratio-matched components. IEEE J. Solid State Circuits Hidetoshi Onodera, Tetsuo Tateishi, Keikichi Tamaru
1987	J	`jnl`	System design of a special-purpose computer for LSI design rule checking. Syst. Comput. Jpn. Keikichi Tamaru, Hidetoshi Onodera
1978	—	`conf`	Development of a high-performance universal computing element - PULCE. AFIPS National Computer Conference Hajime lizuka, Yutaka Hayashi, Keikichi Tamaru, Hisashi Hara