Keiji Kishine - RankMe

62 papers C 3Journal 15Unranked 44

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Trans. Circuits Syst. II Express Briefs Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2024	—	`conf`	A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2024	—	`conf`	A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. SOCC Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2024	J	`jnl`	A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectron. J. Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	J	`jnl`	10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. IEICE Electron. Express Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2023	—	`conf`	4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. ISOCC Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2023	—	`conf`	A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. ICECS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	—	`conf`	High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. ASICON Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	J	`jnl`	Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. IEICE Electron. Express Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2022	—	`conf`	A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. MWSCAS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2022	—	`conf`	A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. ICECS 2022 Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2022	—	`conf`	A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band. ICECS 2022 Masataka Inoue, Shinya Nakashioya, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA. ISOCC Masanao Okamoto, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. MWSCAS Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2022	—	`conf`	A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver. ICEIC Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. ICEIC Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2022	—	`conf`	Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing. ISOCC Shungo Shimohane, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems. ICEIC Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion. ICEIC Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Smart Computational Resource Distribution System with Automatic Classification Interface for CPS. ISOCC Yuuki Teramura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. ASP-DAC Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2021	—	`conf`	5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS. ICEIC Yudai Ichii, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2021	—	`conf`	A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. ICECS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2021	—	`conf`	Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA. ICEIC Ukyo Yoshimura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2021	—	`conf`	Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers. ASP-DAC Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2020	—	`conf`	Processing Time Reduction for JPEG Compression Using Pixel Array Conversion. ISOCC Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2019	—	`conf`	A wideband differential VCO based on double-short-path loop architecture. ISOCC Daisuke Ito, Tomotaka Tanaka, Makoto Nakamura, Keiji Kishine
2019	J	`jnl`	Burst-Mode CMOS Transimpedance Amplifier Based on a Regulated-Cascode Circuit with Gain-Mode Switching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takuya Kojima, Mamoru Kunieda, Makoto Nakamura, Daisuke Ito, Keiji Kishine
2019	—	`conf`	Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier. SoCC Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine
2019	—	`conf`	Frequency Discriminator Using a Simple AD Converter for Interface Systems. ISOCC Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2019	J	`jnl`	Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. IEICE Trans. Electron. Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera
2019	—	`conf`	Optimization Technique of Memory Traffic for FPGA-Based Image Processing System. ISOCC Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara, Keiji Kishine
2019	—	`conf`	Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS. ISOCC Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2018	—	`conf`	A 25-Gb/s 13 mW clock and data recovery using C VLSI-DAT Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka
2018	—	`conf`	A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion. ICECS Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2018	—	`conf`	A Wideband Differential VCO Based on Multiple-path Loop Architecture. ISOCC Tomotaka Tanaka, Fumiya Naito, Makoto Nakamura, Daisuke Ito, Keiji Kishine
2018	—	`conf`	Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. MWSCAS Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2017	C	`conf`	25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. ISCAS Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
2017	—	`conf`	Compact implementation IIR filter in FPGA for noise reduction of sensor signal. ISOCC Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2017	—	`conf`	Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS. ISOCC Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura
2017	—	`conf`	FPGA-based transceiver circuit for labeling signal transmission system. ISOCC Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2016	—	`conf`	36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. ISOCC Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya
2016	—	`conf`	Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS. ISOCC Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, Keiji Kishine
2016	—	`conf`	Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system. ISOCC Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, Keiji Kishine
2015	J	`jnl`	A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera
2014	C	`conf`	A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai
2013	—	`conf`	A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. ASP-DAC Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2013	—	`conf`	Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS. MWSCAS Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Hiroshi Koizumi, Mitsuo Nakamura
2012	—	`conf`	A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. ASP-DAC Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2012	J	`jnl`	Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2012	—	`conf`	Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. MWSCAS Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura
2011	—	`conf`	A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. ISOCC Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2011	—	`conf`	Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. ISOCC Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera
2010	—	`conf`	A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. CICC Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2010	J	`jnl`	Throughput Estimation Method in Burst ACK Scheme for Optimizing Frame Size and Burst Frame Number Appropriate to SNR-Related Error Rate. IEICE Trans. Commun. Shoko Ohteru, Keiji Kishine
2007	J	`jnl`	MAC protocol based on cross-layer design methodology for fast link in wireless communication systems. IEICE Electron. Express Shoko Ohteru, Keiji Kishine, Haruhiko Ichino
2005	J	`jnl`	Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. IEICE Trans. Commun. Kazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino
2004	J	`jnl`	PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. IEEE J. Solid State Circuits Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino
2002	J	`jnl`	Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. IEEE J. Solid State Circuits Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino
2000	C	`conf`	A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. ISCAS Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino
1999	J	`jnl`	A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. IEEE J. Solid State Circuits Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino
1997	J	`jnl`	A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. IEEE J. Solid State Circuits Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino