Kees A. Vissers

83 papers A* 3A 16B 5C 5Misc 8Journal 24Unranked 22

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators. IEEE Trans. Computers Lois Orosa, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos, Juan Gómez-Luna, Michaela Blott, Kees A. Vissers, Onur Mutlu
2022	J	`jnl`	EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators. CoRR Lois Orosa, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos, Juan Gómez-Luna, Michaela Blott, Kees A. Vissers, Onur Mutlu
2022	J	`jnl`	Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning. ACM Trans. Reconfigurable Technol. Syst. Tobias Alonso, Lucian Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, Kees A. Vissers
2022	J	`jnl`	FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Trans. Reconfigurable Technol. Syst. Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees A. Vissers, Zhiru Zhang
2021	B	`conf`	ASLR: An Adaptive Scheduler for Learning Rate. IJCNN Alireza Khodamoradi, Kristof Denolf, Kees A. Vissers, Ryan Kastner
2021	J	`jnl`	Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2021	—	`conf`	Trainable Preprocessing for Reduced Precision Neural Networks. EUSIPCO Gábor Csordás, Kristof Denolf, Nicholas J. Fraser, Alessandro Pappalardo, Kees A. Vissers
2020	A	`conf`	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. ITC Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers
2020	J	`jnl`	FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. CoRR Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers
2020	—	`conf`	Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. HPEC Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar
2020	J	`jnl`	Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. CoRR Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar
2019	Misc	`conf`	Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers
2019	—	`conf`	Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2019	J	`jnl`	Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2019	—	`conf`	Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
2019	J	`jnl`	Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
2019	A	`conf`	Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
2019	—	`conf`	Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs. FPT Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong
2019	A	`conf`	Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP). FPGA Kees A. Vissers
2018	J	`jnl`	FINN- ACM Trans. Reconfigurable Technol. Syst. Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers
2018	—	`conf`	Keynote 2: Versal: The new Xilinx Adaptive Compute Acceleration Platforms (ACAP). IA3@SC Kees A. Vissers
2018	—	`conf`	Novel Neural Network Applications on New Python Enabled Platforms. FPT Kees A. Vissers
2018	J	`jnl`	Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
2017	A	`conf`	FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. FPGA Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
2017	—	`conf`	Scaling Binarized Neural Networks on Reconfigurable Logic. PARMA-DITAM@HiPEAC Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
2017	J	`jnl`	Scaling Binarized Neural Networks on Reconfigurable Logic. CoRR Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
2016	J	`jnl`	FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. CoRR Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers
2015	J	`jnl`	A Hash Table for Line-Rate Data Processing. ACM Trans. Reconfigurable Technol. Syst. Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers
2015	J	`jnl`	Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC. CoRR Daniel Jiménez-González, Carlos Álvarez, Antonio Filgueras, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
2015	Misc	`conf`	Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware. FCCM David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley
2015	—	`conf`	Scaling Out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory. HotStorage Michaela Blott, Ling Liu, Kimon Karras, Kees A. Vissers
2014	J	`jnl`	High-Level Synthesis Case Study: Implementation of a Memcached Server. CoRR Kimon Karras, Michaela Blott, Kees A. Vissers
2014	A	`conf`	OmpSs@Zynq all-programmable SoC ecosystem. FPGA Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
2013	B	`conf`	A flexible hash table design for 10GBPS key-value stores on FPGAS. FPL Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers
2013	—	`conf`	Achieving 10Gbps Line-rate Key-value Stores with FPGAs. HotCloud Michaela Blott, Kimon Karras, Ling Liu, Kees A. Vissers, Jeremia Bär, Zsolt István
2013	—	`conf`	Dataflow architectures for 10Gbps line-rate key-value-stores. Hot Chips Symposium Michaela Blott, Kees A. Vissers
2013	Misc	`conf`	Reconfigurable computing in the era of post-silicon scaling [panel discussion]. FCCM Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek
2013	C	`conf`	Software-programmable digital pre-distortion on the Zynq SoC. VLSI-SoC Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers
2012	—	`conf`	A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). Hot Interconnects John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers
2011	A	`conf`	Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. DATE Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera
2011	A	`conf`	High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). FPGA Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis
2011	J	`jnl`	High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang
2010	A	`conf`	Programming high performance signal processing systems in high level languages. FPGA Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro
2009	A*	`conf`	The wild west: conquest of complex hardware-dependent software design. DAC Hiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees A. Vissers, Marc Serughetti
2009	B	`conf`	Using C-to-gates to program streaming image processing kernels efficiently on FPGAs. FPL Kristof Denolf, Stephen Neuendorffer, Kees A. Vissers
2008	—	`conf`	Streaming Systems in FPGAs. SAMOS Stephen Neuendorffer, Kees A. Vissers
2007	J	`jnl`	A Systematic Approach to Design Low-Power Video Codec Cores. EURASIP J. Embed. Syst. Kristof Denolf, Adrian Chirila-Rus, Paul R. Schumacher, Robert D. Turney, Kees A. Vissers, Diederik Verkest, Henk Corporaal
2007	J	`jnl`	Optimized Generation of Data-Path from C Codes for FPGAs CoRR Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
2006	—	`conf`	The next generation 65-nm FPGA. Hot Chips Symposium Steve Douglass, Kees A. Vissers, Peter Alfke
2005	—	`conf`	A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications. ICIP (2) Paul R. Schumacher, Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Nick Fedele, Kees A. Vissers, Jan Bormans
2005	C	`conf`	Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications. IEEE International Workshop on Rapid System Prototyping Adrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers
2005	A	`conf`	Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). FPGA Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers
2005	J	`jnl`	IEEE-Compliant IDCT on FPGA-Augmented TriMedia. J. VLSI Signal Process. Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
2005	B	`conf`	Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs. FPL Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers
2005	A	`conf`	Optimized Generation of Data-Path from C Codes for FPGAs. DATE Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
2004	A	`conf`	A quantitative analysis of the speedup factors of FPGAs over processors. FPGA Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
2004	J	`jnl`	Pel reconstruction on FPGA-augmented TriMedia. IEEE Trans. Very Large Scale Integr. Syst. Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2004	—	`conf`	Programming Extremely Flexible Platforms. SAMOS Kees A. Vissers
2004	Misc	`conf`	Programming models and architectures for FPGA platforms. CASES Kees A. Vissers
2003	A	`conf`	Panel Title: Reconfigurable Computing - Different Perspectives. DATE Wolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang
2003	A	`conf`	Parallel Processing Architectures for Reconfigurable Systems. DATE Kees A. Vissers
2003	Misc	`conf`	The future of system-level design: can we find the right solutions to the right problems at the right time? CODES+ISSS Reinaldo A. Bergamaschi, Grant Martin, Wayne H. Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris
2002	—	`conf`	A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
2002	—	`conf`	A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. Embedded Processor Design Challenges Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2002	J	`jnl`	Developing Architectural Platforms: A Disciplined Approach. IEEE Des. Test Comput. Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik
2002	B	`conf`	Field-Programmable Custom Computing Machines - A Taxonomy -. FPL Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers
2002	Misc	`conf`	MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. FCCM Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2001	J	`jnl`	A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems. J. VLSI Signal Process. Paul Lieverse, Pieter van der Wolf, Kees A. Vissers, Ed F. Deprettere
2001	Misc	`conf`	An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia. FCCM Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
2001	C	`conf`	MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. ICCD Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2000	A	`conf`	The Future of Flexible HW Platform Architectures Panel Discussion. DATE Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers
2000	A*	`conf`	YAPI: application modeling for signal processing systems. DAC Erwin A. de Kock, W. J. M. Smits, Pieter van der Wolf, Jean-Yves Brunel, W. M. Kruijtzer, Paul Lieverse, Kees A. Vissers, Gerben Essink
1999	—	`conf`	An MPEG-2 decoder case study as a driver for a system level design methodology. CODES Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees A. Vissers
1999	A	`conf`	System level design and debug of high-performance embedded media systems (tutorial). ICCAD Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar
1999	C	`conf`	TriMedia CPU64 Application Domain and Benchmark Suite. ICCD A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans
1999	C	`conf`	TriMedia CPU64 Architecture. ICCD Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel
1998	Misc	`conf`	Design space exploration for future TriMedia CPUs. ICASSP Frans Sijstermans, Evert-Jan D. Pol, Bram Riemens, Kees A. Vissers, Selliah Rathnam, Gert Slavenburg
1998	—	`conf`	The construction of a retargetable simulator for an architecture template. CODES Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
1997	—	`conf`	An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
1997	—	`conf`	Trade-offs in the design of mixed hardware-software systems-a perspective from industry. CODES Kees A. Vissers
1995	J	`jnl`	Architecture and programming of two generations video signal processors. Microprocess. Microprogramming Kees A. Vissers, Gerben Essink, Piet J. van Gerwen, P. J. M. Janssen, O. Popp, E. Riddersma, W. J. M. Smits, Harry J. M. Veendrick
1991	A*	`conf`	Architecture and Programming of a VLIW Style Programmable Video Signal Processor. MICRO Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers
1991	A	`conf`	Scheduling in Programmable Video Signal Processors. ICCAD Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers