Keerthi Heragu

16 papers A* 1A 2Misc 7Journal 4Unranked 1
YearRankTypeTitle / Venue / Authors
2008 — conf
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques.
ISSCC
Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko
2005 J jnl
A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels.
IEEE J. Solid State Circuits
Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee
2002 J jnl
Test vector generation for charge sharing failures in dynamic logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton
2001 Misc conf
Testing of Dynamic Logic Circuits Based on Charge Sharing.
VTS
Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton
1999 Misc conf
A Test Generator for Segment Delay Faults.
VLSI Design
Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1998 — —
New Techniques to Verify Timing Correctness of Integrated Circuits
Keerthi Heragu
1998 Misc conf
Where We Might Stumble with Embedded-System Test.
VTS
Keerthi Heragu
1997 A conf
Fast identification of untestable delay faults using implications.
ICCAD
Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1997 J jnl
Improving a nonenumerative method to estimate path delay fault coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
1996 Misc conf
Improving accuracy in path delay fault coverage estimation.
VLSI Design
Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996 A conf
SIGMA: a simulator for segment delay faults.
ICCAD
Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996 Misc conf
Segment delay faults: a new fault model.
VTS
Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1995 J jnl
Fault coverage estimation by test vector sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1995 Misc conf
Statistical methods for delay fault coverage analysis.
VLSI Design
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
1994 A* conf
An Efficient Path Delay Fault Coverage Estimator.
DAC
Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
1994 Misc conf
FACTS: fault coverage estimation by test vector sampling.
VTS
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell