Ke Wang

24 papers A* 5A 3C 2Journal 12Unranked 2
YearRankTypeTitle / Venue / Authors
2025 A conf
A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional Networks.
DATE
Yingnan Zhao, Ke Wang, Ahmed Louri
2025 — conf
Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults.
DFT
Youssef A. Ait Alama, Sampada Sakpal, Ke Wang, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri
2025 J jnl
FORT-GCN: A Fault-Tolerant and Adaptive Accelerator Design for Efficient Graph Convolutional Network Inference.
ACM Trans. Embed. Comput. Syst.
Ke Wang, Yingnan Zhao, Ahmed Louri
2025 J jnl
HS-GCN: A High-Performance, Sustainable, and Scalable Chiplet-Based Accelerator for Graph Convolutional Network Inference.
IEEE Trans. Sustain. Comput.
Yingnan Zhao, Ke Wang, Ahmed Louri
2025 — conf
Learning-Enabled Denial-of-Service (DoS) Attack Detection and Mitigation for Chiplet-Based Hybrid Interconnection Network.
ACM Great Lakes Symposium on VLSI
Md. Tareq Mahmud, Ke Wang
2024 J jnl
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems.
IEEE Comput. Archit. Lett.
Md. Tareq Mahmud, Ke Wang
2024 J jnl
Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults.
CoRR
Youssef A. Ait Alama, Sampada Sakpal, Ke Wang, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri
2024 A* conf
An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference.
DAC
Yingnan Zhao, Ke Wang, Jiaqi Yang, Ahmed Louri
2024 J jnl
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration.
IEEE Trans. Sustain. Comput.
Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri
2024 J jnl
OPT-GCN: A Unified and Scalable Chiplet-Based Accelerator for High-Performance and Energy-Efficient GCN Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yingnan Zhao, Ke Wang, Ahmed Louri
2023 A* conf
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations.
ISCA
Jiajun Li, Yuxuan Zhang, Hao Zheng, Ke Wang
2023 J jnl
GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators.
J. Comput. Sci. Technol.
Jiajun Li, Ke Wang, Hao Zheng, Ahmed Louri
2023 C conf
Simulation Study of Ferroresonance on Secondary Side of Main Transformer in a 500kV System.
iSPEC
Chuanzong Zhu, Shichang Li, Yong Li, Jiajun Li, Gang Li, Ke Wang, Yifeng Shi
2022 A conf
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems.
DATE
Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri
2022 J jnl
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth
2022 C conf
FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture.
ICCD
Yingnan Zhao, Ke Wang, Ahmed Louri
2022 J jnl
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing.
IEEE Trans. Parallel Distributed Syst.
Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri
2022 J jnl
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design.
IEEE Trans. Sustain. Comput.
Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri
2021 A* conf
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures.
HPCA
Hao Zheng, Ke Wang, Ahmed Louri
2020 A* conf
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures.
DAC
Hao Zheng, Ke Wang, Ahmed Louri
2020 J jnl
CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning.
IEEE Trans. Parallel Distributed Syst.
Ke Wang, Ahmed Louri
2020 J jnl
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture.
IEEE Micro
Ke Wang, Hao Zheng, Ahmed Louri
2019 A conf
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin.
DATE
Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2019 A* conf
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores.
ISCA
Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu