Ke Huang

11 papers C 2Journal 2Unranked 7
YearRankTypeTitle / Venue / Authors
2015 — conf
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology.
CICC
Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
2015 — conf
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS.
NEWCAS
Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang
2015 J jnl
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2014 J jnl
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang
2014 — conf
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology.
CICC
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2013 — conf
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology.
ASICON
Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang
2013 — conf
A 10Gb/s analog equalizer in 0.18um CMOS.
ASICON
Linghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang
2013 — conf
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.
VLSI-DAT
Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang
2012 C conf
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS.
ISCAS
Shijie Hu, Chen Jia, Ke Huang, Chun Zhang, Xuqiang Zheng, Zhihua Wang
2012 C conf
A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology.
ISCAS
Ke Huang, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee, Zhihua Wang
2012 — conf
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS.
MWSCAS
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang