Kazuyuki Nakamura

35 papers A 1C 4Misc 1Journal 20Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	The Application of Zig-Zag Sampler in Sequential Markov Chain Monte Carlo. J. Inf. Process. Yu Han, Kazuyuki Nakamura
2024	J	`jnl`	Aortic root landmark localization with optimal transport loss for heatmap regression. CoRR Tsuyoshi Ishizone, Masaki Miyasaka, Sae Ochi, Norio Tada, Kazuyuki Nakamura
2023	J	`jnl`	Effective mechanical potential of cell-cell interaction explains three-dimensional morphologies during early embryogenesis. PLoS Comput. Biol. Hiroshi Koyama, Hisashi Okumura, Atsushi M. Ito, Kazuyuki Nakamura, Tetsuhisa Otani, Kagayaki Kato, Toshihiko Fujimori
2022	C	`conf`	An Online System of Detecting Anomalies and Estimating Cycle Times for Production Lines. IECON Tsuyoshi Ishizone, Tomoyuki Higuchi, Kosuke Okusa, Kazuyuki Nakamura
2022	C	`conf`	Occupancy Detection for General Households by Bidirectional LSTM with Attention. IECON Hisashi Oshima, Tsuyoshi Ishizone, Kazuyuki Nakamura, Tomoyuki Higuchi
2022	J	`jnl`	Real-time Linear Operator Construction and State Estimation with the Kalman Filter. J. Inf. Process. Tsuyoshi Ishizone, Kazuyuki Nakamura
2021	J	`jnl`	The Application of Zig-Zag Sampler in Sequential Markov Chain Monte Carlo. CoRR Yu Han, Kazuyuki Nakamura
2020	J	`jnl`	Ensemble Kalman Variational Objectives: Nonlinear Latent Trajectory Inference with A Hybrid of Variational Inference and Ensemble Kalman Filter. CoRR Tsuyoshi Ishizone, Tomoyuki Higuchi, Kazuyuki Nakamura
2020	—	`conf`	Identifying Snowfall Clouds at Syowa Station, Antarctica via a Convolutional Neural Network. JSAI Kazue Suzuki, Masaki Shimomura, Kazuyuki Nakamura, Naohiko Hirasawa, Hironori Yabuki, Takashi Yamanouchi, Terumasa Tokunaga
2018	—	`conf`	Multiresolutional Hierarchical Bayesian NMF for Detailed Audio Analysis of Music Performances. APSIPA Takeshi Hori, Kazuyuki Nakamura, Shigeki Sagayama
2017	—	`conf`	Music chord recognition from audio data using bidirectional encoder-decoder LSTMs. APSIPA Takeshi Hori, Kazuyuki Nakamura, Shigeki Sagayama
2012	—	`conf`	Extraction of groove feelings from drum data using non-negative matrix factorization. SCIS&ISIS Yoshito Ohya, Kazuyuki Nakamura, Terumasa Tokunaga
2012	C	`conf`	Instability caused by the cubic potential in the foreign exchange market observed at the intervention by the Bank of Japan. FUSION Yoshihiro Yura, Misako Takayasu, Hideki Takayasu, Kazuyuki Nakamura
2011	J	`jnl`	An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O. IEICE Trans. Electron. Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura
2011	C	`conf`	Sequential data assimilation in geotechnical engineering and its application to seepage analysis. FUSION Kazuyuki Nakamura, Shinya Yamamoto, Makoto Honda
2010	—	`conf`	A Knowledge Sharing System for Software Developers. ICSOFT (2) Takayuki Shibata, Kazuyuki Nakamura, Takanobu Sato, Rentaro Yoshioka
2010	—	`conf`	An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function. ASP-DAC Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura
2009	Misc	`conf`	Parameter Estimation of In Silico Biological Pathways with Particle Filtering Towards a Petascale Computing. Pacific Symposium on Biocomputing Kazuyuki Nakamura, Ryo Yoshida, Masao Nagasaki, Satoru Miyano, Tomoyuki Higuchi
2007	J	`jnl`	A Recursive Recomputation Approach for Smoothing in Nonlinear State-Space Modeling: An Attempt for Reducing Space Complexity. IEEE Trans. Signal Process. Kazuyuki Nakamura, Takashi Tsuchiya
2006	J	`jnl`	Sequential Data Assimilation: Information Fusion of a Numerical Simulation and Large Scale Observation Data. J. Univers. Comput. Sci. Kazuyuki Nakamura, Tomoyuki Higuchi, Naoki Hirose
2005	—	`conf`	An Improvement of ITU-T G.711 Packet Loss Concealment. EuroIMSA Keiichi Funaki, Kazuyuki Nakamura
2001	—	`conf`	A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina
2001	J	`jnl`	A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture. IEEE J. Solid State Circuits Kouichi Yamaguchi, Muneo Fukaishi, Takehiko Sakamoto, Naoto Akiyama, Kazuyuki Nakamura
2001	—	`conf`	Optical interconnection as an IP macro of a CMOS library. Hot Interconnects Takashi Yoshikawa, Ichiro Hatakeyama, Kazunori Miyoshi, Kazuhiko Kurata, Juni-Ichi Sasaki, Nobuharu Kami, Takara Sugimoto, Muneo Fukaishi, Kazuyuki Nakamura, Kei Tanaka, Hiroaki Nishi, Tomohiro Kudoh
2001	A	`conf`	Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations. ISLPED Takeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura
2000	J	`jnl`	A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays. IEEE J. Solid State Circuits Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi
1998	J	`jnl`	A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture. IEEE J. Solid State Circuits Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi
1997	J	`jnl`	A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. IEEE J. Solid State Circuits Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto
1996	J	`jnl`	A 3.84 gips integrated memory array processor. Syst. Comput. Jpn. Yoshihiro Fujita, Nobuyuki Yamashita, Tohru Kimura, Kazuyuki Nakamura, Shin'ichiro Okazaki
1996	J	`jnl`	A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki
1995	J	`jnl`	Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina
1994	J	`jnl`	A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. IEEE J. Solid State Circuits Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki
1994	J	`jnl`	A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. IEEE J. Solid State Circuits Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina
1992	J	`jnl`	A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits Kazuyuki Nakamura, Takashi Oguri, Takao Atsumo, Masahide Takada, Atsushi Ikemoto, Hisamitsu Suzuki, Tadashi Nishigori, Tohru Yamazaki
1990	J	`jnl`	A 5-ns 1-Mb ECL BiCMOS SRAM. IEEE J. Solid State Circuits Masahide Takada, Kazuyuki Nakamura, Toshio Takeshima, Koichiro Furuta, Tohru Yamazaki, Kiyotaka Imai, Susumu Ohi, Yumi Sekine, Yukio Minato, Hisamitsu Kimuto