Kazuyoshi Takagi

40 papers A 2C 3Misc 1Journal 27Unranked 7
YearRankTypeTitle / Venue / Authors
2021 J jnl
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao
2020 J jnl
mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices.
J. Inf. Process.
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
2019 J jnl
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.
IPSJ Trans. Syst. LSI Des. Methodol.
Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi
2019 J jnl
Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing.
IEICE Trans. Electron.
Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi
2019 — conf
mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices.
HEART
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
2018 J jnl
Algorithms for Evaluating the Matrix Polynomial
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi
2018 Misc conf
Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress.
EMSOFT
Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi
2018 A conf
Multi-terminal routing with length-matching for rapid single flux quantum circuits.
ICCAD
Pei-Yi Cheng, Kazuyoshi Takagi, Tsung-Yi Ho
2016 — conf
An evaluation framework of OS-level power managements for the big.LITTLE architecture.
NEWCAS
Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi
2016 J jnl
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation.
IEICE Trans. Electron.
Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi
2016 J jnl
RSFQ 4-bit Bit-Slice Integer Multiplier.
IEICE Trans. Electron.
Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi
2015 J jnl
A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi
2015 J jnl
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.
Inf. Media Technol.
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2015 J jnl
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.
IPSJ Trans. Syst. LSI Des. Methodol.
Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2014 — conf
An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality.
HPCC/CSS/ICESS
Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2014 J jnl
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits.
IEICE Trans. Electron.
Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi
2014 J jnl
Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm
IEICE Trans. Electron.
Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka
2014 J jnl
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors.
IEICE Trans. Electron.
Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi
2014 J jnl
Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation.
IEICE Trans. Electron.
Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi
2014 J jnl
Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2013 — conf
A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis.
ICA3PP (1)
Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
2012 J jnl
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition.
IEICE Trans. Electron.
Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
2012 J jnl
Fast inversion algorithm in GF(2
IET Comput. Digit. Tech.
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
2011 J jnl
Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits.
IEICE Trans. Electron.
Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi
2010 J jnl
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing.
IEICE Trans. Inf. Syst.
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
2010 J jnl
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm.
IEICE Trans. Electron.
Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki
2008 J jnl
A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
2008 C conf
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.
ISCAS
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi
2007 J jnl
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.
IEICE Trans. Electron.
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
2007 C conf
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2).
IEEE Symposium on Computer Arithmetic
Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi
2007 J jnl
Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koji Obata, Kazuyoshi Takagi, Naofumi Takagi
2007 — conf
VLSI CAD Education and Exercise Course with Public Domain Tools.
MSE
Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada
2006 J jnl
A Hardware Algorithm for Integer Division Using the SD2 Representation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
2006 — conf
A transduction-based framework to synthesize RSFQ circuits.
ASP-DAC
Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi
2005 C conf
A Hardware Algorithm for Integer Division.
IEEE Symposium on Computer Arithmetic
Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi
2003 J jnl
Digit-Recurrence Algorithm for Computing Reciprocal Square-Root.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi
2002 J jnl
A VLSI Algorithm for Division in GF(2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi
2001 J jnl
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis.
IEEE Trans. Computers
Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi
2000 — conf
An application specific Java processor with reconfigurabilities.
ASP-DAC
Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe
1998 A conf
Waiting false path analysis of sequential logic circuits for performance optimization.
ICCAD
Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe