Kazuyasu Fujishima

22 papers A 3Journal 19

Year	Rank	Type	Title / Venue / Authors
2005	J	`jnl`	A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2000	J	`jnl`	High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara
1994	J	`jnl`	A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1994	J	`jnl`	An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE J. Solid State Circuits Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara
1994	J	`jnl`	An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara
1993	J	`jnl`	Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
1992	J	`jnl`	A 34-ns 16-Mb DRAM with controllable voltage down-converter. IEEE J. Solid State Circuits Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima
1992	A	`conf`	A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
1992	J	`jnl`	A dual-mode sensing scheme of capacitor-coupled EEPROM cell. IEEE J. Solid State Circuits Masanori Hayashikoshi, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1992	J	`jnl`	A high-density dual-port memory cell operation and array architecture for ULSI DRAMs. IEEE J. Solid State Circuits Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1992	J	`jnl`	Cell-plate line connecting complementary bit-line (C IEEE J. Solid State Circuits Mikio Asakura, Kazutami Arimoto, Hideto Hidaka, Kazuyasu Fujishima
1991	J	`jnl`	A circuit design of intelligent cache DRAM with automatic write-back capability. IEEE J. Solid State Circuits Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima
1991	J	`jnl`	A divided/shared bit-line sensing scheme for ULSI DRAM cores. IEEE J. Solid State Circuits Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima
1990	J	`jnl`	An experimental 1-Mbit cache DRAM with ECC. IEEE J. Solid State Circuits Mikio Asakura, Yoshio Matsuda, Hidaka Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima
1990	J	`jnl`	The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima
1989	J	`jnl`	A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano
1989	A	`conf`	A New Array Architecture for Parallel Testing in VLSI Memories. ITC Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
1989	J	`jnl`	A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. IEEE J. Solid State Circuits Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima
1989	J	`jnl`	Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid State Circuits Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara
1986	A	`conf`	Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. ITC Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka