Kazuya Masu - RankMe

104 papers A* 1A 1B 3C 5Misc 1Journal 43Unranked 50

Year	Rank	Type	Title / Venue / Authors
2021	—	`conf`	A Simplified Analytical Damping Constant Model for Perforated Proof Mass Structure of MEMS Capacitive Accelerometer by Multi-Layer Metal Technology. IEEE SENSORS Kohei Shibata, Akihiro Uchiyama, Akira Onishi, Shinichi Iida, Toshifumi Konishi, Noboru Ishihara, Katsuyuki Machida, Kazuya Masu, Hiroyuki Ito
2020	J	`jnl`	Distributed Sensing Via Inductively Coupled Single-Transistor Chaotic Oscillators: A New Approach and Its Experimental Proof-of-Concept. IEEE Access Ludovico Minati, Korkut Kaan Tokgoz, Mattia Frasca, Yasuharu Koike, Jacopo Iannacci, Natsue Yoshimura, Kazuya Masu, Hiroyuki Ito
2019	J	`jnl`	Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades. IEEE Access Ludovico Minati, Mattia Frasca, Natsue Yoshimura, Leonardo Ricci, Pawel Oswiecimka, Yasuharu Koike, Kazuya Masu, Hiroyuki Ito
2019	—	`conf`	Fabrication of Au-Cu Alloy/Ti Layered Micro-Cantilevers and the Long-Term Structure Stability. IEEE SENSORS Kyotaro Nitta, Masato Sone, Haochun Tang, Chun-Yi Chen, Tso-Fu Mark Chang, Daisuke Yamane, Shinichi Iida, Katsuyuki Machida, Hiroyuki Ito, Kazuya Masu
2019	—	`conf`	High-Sensitivity Inertial Sensor Module to Measure Hidden Micro Muscular Sounds. BioCAS Tatsuya Koga, Katsuyuki Machida, Yoshihiro Miyake, Kazuya Masu, Takashi Ichikawa, Naoto Tanaka, Taiki Ogata, Hiroki Ora, Daisuke Yamane, Noboru Ishihara, Hiroyuki Ito, Masato Sone
2018	J	`jnl`	A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers. IEICE Electron. Express Motohiro Takayasu, Shiro Dosho, Hiroyuki Ito, Daisuke Yamane, Toshifumi Konishi, Katsuyuki Machida, Noboru Ishihara, Kazuya Masu
2017	J	`jnl`	A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique. IEEE J. Solid State Circuits Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2017	—	`conf`	A study on young's modulus of electroplated gold cantilevers for MEMS devices. NEMS Hideaki Nakajima, Tso-Fu Mark Chang, Chun-Yi Chen, Toshifumi Konishi, Katsuyuki Machida, Hiroshi Toshiyoshi, Daisuke Yamane, Kazuya Masu, Masato Sone
2017	—	`conf`	Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. ASP-DAC Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2017	—	`conf`	Estimation of energy self-sufficiency rate by EMS simulation using SPICE. ICTC Yuta Oshima, Iwao Mizumoto, Hiroshi Oguma, Noboru Ishihara, Kazuya Masu
2016	—	`conf`	A damping constant model for proof-mass structure design of MEMS inertial sensor by multi-layer metal technology. IEEE SENSORS Toshifumi Konishi, Teruaki Safu, Katsuyuki Machida, Daisuke Yamane, Masato Sone, Kazuya Masu, Hiroshi Toshiyoshi
2016	—	`conf`	A design of spring constant arranged for MEMS accelerometer by multi-layer metal technology. NEMS Daisuke Yamane, Toshifumi Konishi, Teruaki Safu, Hiroshi Toshiyoshi, Masato Sone, Kazuya Masu, Katsuyuki Machida
2016	—	`conf`	An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. VLSI Circuits Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2016	—	`conf`	Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's disease. ESSCIRC Kazuya Masu, Daisuke Yamane, Katsuyuki Machida, Masato Sone, Yoshihiro Miyake
2016	—	`conf`	Environmental Data Recovery using Polynomial Regression for Large-scale Wireless Sensor Networks. SENSORNETS Kohei Ohba, Yoshihiro Yoneda, Koji Kurihara, Takashi Suganuma, Hiroyuki Ito, Noboru Ishihara, Kunihiko Gotoh, Koichiro Yamashita, Kazuya Masu
2016	J	`jnl`	Evaluation and modeling of adhesion layer in shock-protection structure for MEMS accelerometer. Microelectron. Reliab. Daisuke Yamane, Toshifumi Konishi, Teruaki Safu, Hiroshi Toshiyoshi, Masato Sone, Kazuya Masu, Katsuyuki Machida
2016	J	`jnl`	Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato
2016	—	`conf`	Simulation and evaluation of PV power generation for energy management system using SPICE. ICTC Yuta Oshima, Hiroshi Oguma, Noboru Ishihara, Kazuya Masu
2015	—	`conf`	13.8 A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique. ISSCC Atsushi Shirane, Haowei Tan, Yiming Fang, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2015	C	`conf`	A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna. ISCAS Yosuke Ishikawa, Sang-yeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2015	—	`conf`	A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network. ASP-DAC Sho Ikeda, Sang-yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2015	J	`jnl`	RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter. IEEE J. Solid State Circuits Atsushi Shirane, Yiming Fang, Haowei Tan, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	—	`conf`	A 0.5-V 2.5-GHz high-gain low-power regenerative amplifier based on Colpitts oscillator topology in 65-nm CMOS. APCCAS Taisuke Hamada, Hao Jiang, Yiming Fang, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	—	`conf`	A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET. A-SSCC Sho Ikeda, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	—	`conf`	A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor. ASP-DAC Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	J	`jnl`	A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS. IEICE Trans. Electron. Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	J	`jnl`	A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
2014	C	`conf`	An ultra low power pH-monitoring IC with a duty-cycling wireless FM-transmitter. ISCAS Yusuke Shiino, Hiroyuki Ito, Taku Fujiwara, Noboru Ishihara, Hisashi Yamanouchi, Hiroki Tanabe, Satoshi Nomura, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu
2014	—	`conf`	An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI. A-SSCC Hiroyuki Ito, Yoshihiro Yoneda, Taiki Ibe, Taisuke Hamada, Noboru Ishihara, Kazuya Masu, Shoichi Masui, Youichi Momiyama
2014	J	`jnl`	Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis. IEICE Trans. Electron. Shiho Hagiwara, Takanori Date, Kazuya Masu, Takashi Sato
2014	J	`jnl`	State-Dependence of On-Chip Power Distribution Network Capacitance. IEICE Trans. Electron. Koh Yamanaga, Shiho Hagiwara, Ryo Takahashi, Kazuya Masu, Takashi Sato
2013	J	`jnl`	A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate. IEICE Electron. Express Hamid Kiumarsi, Hiroyuki Ito, Kenichi Okada, Yusuke Uemichi, Yasuto Chiba, Noboru Ishihara, Kazuya Masu
2013	—	`conf`	A mixed-design technique for integrated MEMS using a circuit simulator with HDL. MIXDES Hiroshi Toshiyoshi, Toshifumi Konishi, Katsuyuki Machida, Kazuya Masu
2013	—	`conf`	A process-scalable RF transmitter using 90nm and 65nm Si CMOS. VLSI-DAT Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2013	—	`conf`	Challenges in integration of diverse functionalities on CMOS. ASP-DAC Kazuya Masu, Noboru Ishihara, Toshifumi Konishi, Katsuyuki Machida, Hiroshi Toshiyoshi
2012	J	`jnl`	A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. IEICE Trans. Electron. Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2012	J	`jnl`	Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique. IEICE Electron. Express Sang-yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu
2012	—	`conf`	Optimal design method for chip-area-efficient CMOS low-dropout regulator. APCCAS Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2012	J	`jnl`	RF signal generator using time domain harmonic suppression technique in 90nm CMOS. IEICE Electron. Express Kazuo Nakano, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
2011	—	`conf`	A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS. ISOCC Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2011	J	`jnl`	A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers. J. Electr. Comput. Eng. Yusaku Ito, Kenichi Okada, Kazuya Masu
2011	—	`conf`	A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. ISOCC Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2011	J	`jnl`	RF CMOS Integrated Circuit: History, Current Status and Future Prospects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Noboru Ishihara, Shuhei Amakawa, Kazuya Masu
2010	J	`jnl`	A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. IEICE Trans. Electron. Takumi Uezono, Kazuya Masu, Takashi Sato
2010	J	`jnl`	A Universal Equivalent Circuit Model for Ceramic Capacitors. IEICE Trans. Electron. Koh Yamanaga, Shuhei Amakawa, Kazuya Masu, Takashi Sato
2010	J	`jnl`	A study for the efficiency of transmission energy for different high-frequency communication circuits. IEICE Electron. Express Toshiyuki Umeda, Kazuya Masu
2010	—	`conf`	Application of generalized scattering matrix for prediction of power supply noise. SLIP Koh Yamanaga, Kazuya Masu, Takashi Sato
2010	C	`conf`	Decomposition of drain-current variation into gain-factor and threshold voltage variations. ISCAS Takashi Sato, Takumi Uezono, Noriaki Nakayama, Kazuya Masu
2010	J	`jnl`	Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato
2010	—	`conf`	Linear time calculation of state-dependent power distribution network capacitance. ISQED Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato
2010	Misc	`conf`	Path clustering for adaptive test. VTS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	—	`conf`	Robust importance sampling for efficient SRAM yield analysis. ISQED Takanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato
2010	C	`conf`	Scan based process parameter estimation through path-delay inequalities. ISCAS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	J	`jnl`	Wide-band, high linear low noise amplifier design in 0.18um CMOS technology. IEICE Electron. Express Mousa M. Othman, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
2009	J	`jnl`	2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koh Yamanaga, Takashi Sato, Kazuya Masu
2009	—	`conf`	A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS. ESSCIRC Yuka Kobayashi, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
2009	J	`jnl`	Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. IEEE J. Solid State Circuits Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu
2009	—	`conf`	An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
2009	J	`jnl`	Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shiho Hagiwara, Takashi Sato, Kazuya Masu
2009	J	`jnl`	Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Takeshi Ito, Kenichi Okada, Kazuya Masu
2009	—	`conf`	Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique. ECCTD Tomoaki Maekawa, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu
2009	J	`jnl`	One-Shot Voltage-Measurement Circuit Utilizing Process Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Uezono, Takashi Sato, Kazuya Masu
2009	J	`jnl`	Physical design challenges to nano-CMOS circuits. IEICE Electron. Express Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa
2009	J	`jnl`	Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hirotaka Sugawara, Kenichi Okada, Kazuya Masu
2008	—	`conf`	A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. ESSCIRC Hiroyuki Ito, Hasnain Lakdawala, Ashoke Ravi, Stefano Pellerano, Rick Ruby, Krishnamurthy Soumyanath, Kazuya Masu
2008	J	`jnl`	A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. IEEE J. Solid State Circuits Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu
2008	—	`conf`	An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx. ESSCIRC Tomoaki Maekawa, Hiroyuki Ito, Kazuya Masu
2008	J	`jnl`	An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu
2008	J	`jnl`	Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
2008	—	`conf`	Determination of optimal polynomial regression function to decompose on-die systematic and random variations. ASP-DAC Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu
2008	—	`conf`	LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. ASP-DAC Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu
2008	J	`jnl`	Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Trans. Electron. Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro
2008	A*	`conf`	Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. DAC Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu
2008	J	`jnl`	Physical Modeling of MEMS Variable Inductor. IEEE Trans. Circuits Syst. II Express Briefs Tackya Yammouch, Kenichi Okada, Kazuya Masu
2008	J	`jnl`	Reconfigurable RF CMOS Circuit for Cognitive Radio. IEICE Trans. Commun. Kazuya Masu, Kenichi Okada
2008	—	`conf`	Small-area CMOS RF distributed mixer using multi-port inductors. ASP-DAC Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2007	—	`conf`	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu
2007	—	`conf`	A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu
2007	—	`conf`	A Wideband CMOS LC-VCO Using Variable Inductor. ASP-DAC Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu
2007	—	`conf`	Adaptable wire-length distribution with tunable occupation probability. SLIP Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu
2007	—	`conf`	Improvement of power distribution network using correlation-based regression analysis. ACM Great Lakes Symposium on VLSI Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
2007	J	`jnl`	Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology. IEICE Trans. Electron. Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, Kazuya Masu
2007	—	`conf`	Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. ASP-DAC Satoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu
2007	—	`conf`	Weakness Identification for Effective Repair of Power Distribution Network. PATMOS Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu
2006	—	`conf`	Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. PATMOS Kenichi Okada, Takumi Uezono, Kazuya Masu
2006	J	`jnl`	RF Passive Components Using Metal Line on Si CMOS. IEICE Trans. Electron. Kazuya Masu, Kenichi Okada, Hiroyuki Ito
2006	C	`conf`	Reconfigurable CMOS low noise amplifier for self compensation. ISCAS D. Kawazoe, Hirotaka Sugawara, Tatsuya Ito, Kenichi Okada, Kazuya Masu
2006	J	`jnl`	Statistical Modeling of a Via Distribution for Yield Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Uezono, Kenichi Okada, Kazuya Masu
2006	—	`conf`	Via Distribution Model for Yield Estimation. ISQED Takumi Uezono, Kenichi Okada, Kazuya Masu
2005	—	`conf`	A dynamic reconfigurable RF circuit architecture. ASP-DAC Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu
2005	J	`jnl`	Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
2005	J	`jnl`	Evaluation of X Architecture Using Interconnect Length Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu
2005	—	`conf`	Evaluation of on-chip transmission line interconnect using wire length distribution. ASP-DAC Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu
2005	—	`conf`	Prediction of delay time for future LSI using on-chip transmission line interconnects. SLIP Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu
2005	J	`jnl`	Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2005	—	`conf`	Wire Length Distribution Model Considering Core Utilization for System on Chip. ISVLSI Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
2005	J	`jnl`	Wire Length Distribution Model for System LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu
2004	—	`conf`	Differential transmission line interconnect for high speed and low power global wiring. CICC Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2004	—	`conf`	High speed and low power on-chip micro network circuit with differential transmission line. SoC Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Kazuya Masu
2004	J	`jnl`	Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. IEICE Electron. Express Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu
2004	A	`conf`	ULSI Interconnect Length Distribution Model Considering Core Utilization. DATE Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
2000	B	`conf`	Design and implementation of intracell reverse link using approximately synchronized CDMA. PIMRC Suguru Kameda, Kouichi Takahashi, Taketo Kamata, Jae Sang Cha, Hiroyuki Nakase, Kazuya Masu, Kazuo Tsubouchi
2000	B	`conf`	Implementation of low power matched filter LSI for IMT-2000. PIMRC Hiroyuki Nakase, Koji Kubota, Suguru Kameda, Kenji Togura, Kazuya Masu, Kazuo Tsubouchi
1994	B	`conf`	One chip demodulator using RF front-end SAW correlator for 2.4 GHz asynchronous spread spectrum modem. PIMRC Hiroyuki Nakase, T. Kasai, Y. Nakamura, Kazuya Masu, Kazuo Tsubouchi